參數(shù)資料
型號(hào): X9259US24ZT1
廠商: Intersil
文件頁數(shù): 19/21頁
文件大?。?/td> 0K
描述: IC XDCP QUAD 256TAP 50K 24-SOIC
標(biāo)準(zhǔn)包裝: 1,000
系列: XDCP™
接片: 256
電阻(歐姆): 50k
電路數(shù): 4
溫度系數(shù): 標(biāo)準(zhǔn)值 ±300 ppm/°C
存儲(chǔ)器類型: 非易失
接口: I²C(設(shè)備位址)
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 24-SOIC
包裝: 帶卷 (TR)
7
FN8169.5
April 13, 2007
Identification Byte
The first byte sent to the X9259 from the host is called the
Identification Byte. The most significant four bits are a
Device Type Identifier, ID[3:0] bits, which must be 0101.
Refer to Table 3.
Only the device which Slave Address matches the incoming
device address sent by the master executes the instruction.
The A3 - A0 inputs can be actively driven by CMOS input
signals or tied to VCC or VSS.
INSTRUCTION BYTE (I)
The next byte sent to the X9259 contains the instruction and
register pointer information. The four most significant bits are
used provide the instruction opcode I [3:0]. The RB and RA
bits point to one of the four data registers of each associated
XDCP. The least two significant bits point to one of four
Wiper Counter Registers or DCPs. The format is shown in
Table 4.
Data Register Selection
#: 0, 1, 2, or 3
The least significant four bits of the Identification Byte are
the Slave Address bits, AD[3:0]. To access the X9259, these
four bits must match the logic values of pins A3, A2, A1, and
A0.
SDA
SCL
START
DATA
STOP
STABLE
CHANGE
DATA
STABLE
FIGURE 2. VALID DATA CHANGES, START, AND STOP CONDITIONS
SDA OUTPUT FROM
TRANSMITTER
SDA OUTPUT FROM
RECEIVER
8
1
9
START
ACK
SCL FROM
MASTER
FIGURE 3. ACKNOWLEDGE RESPONSE FROM RECEIVER
REGISTER
RB
RA
DR#0
0
DR#1
0
1
DR#2
1
0
DR#3
1
X9259
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