參數(shù)資料
型號(hào): X9258US24-2.7
元件分類(lèi): 數(shù)字電位計(jì)
英文描述: Quad Digital Controlled Potentiometers (XDCP)
中文描述: 四數(shù)字(數(shù)字電位器控制電位器)
文件頁(yè)數(shù): 9/22頁(yè)
文件大小: 413K
代理商: X9258US24-2.7
X9258
Characteristics subject to change without notice.
9 of 22
REV 1.1.7 2/4/03
www.xicor.com
REGISTER DESCRIPTIONS
Data Registers, (8-Bit), Nonvolatile
WP7
WP6
WP5
NV
NV
NV
(MSB)
Four 8-bit Data Registers for each DCP. (sixteen 8-bit
registers in total).
– {D7~D0}: These bits are for general purpose not
volatile data storage or for storage of up to four
different wiper values. The contents of Data Register
0 are automatically moved to the wiper counter
register on power-up.
Wiper Counter Register, (8-Bit), Volatile
WP7
WP6
WP5
V
V
V
(MSB)
One 8-bit Wiper Counter Register for each DCP. (Four
8-bit registers in total.)
– {D7~D0}: These bits specify the wiper position of the
respective DCP. The Wiper Counter Register is
loaded on power-up by the value in Data Register 0.
The contents of the WCR can be loaded from any of
the other Data Register or directly. The contents of
the WCR can be saved in a DR.
WP4
NV
WP3
NV
WP2
NV
WP1
NV
WP0
NV
(LSB)
WP4
V
WP3
V
WP2
V
WP1
V
WP0
V
(LSB)
Instruction Format
Notes:
(1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.
(2) “A3 ~ A0”: stands for the device addresses sent by the master.
(3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
(4) “I”: stands for the increment operation, SDA held high during active SCL phase (high).
(5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).
Read Wiper Counter Register (WCR)
Write Wiper Counter Register (WCR)
Read Data Register (DR)
S
T
A
R
T
device type
identifier
device
addresses
S
A
C
K
instruction
opcode
WCR
addresses
S
A
C
K
wiper position
(sent by slave on SDA)
M
A
C
K
S
T
O
P
0
1
0
1
A
3
A
2
A
1
A
0
1
0
0
1
0
0
P
1
P
0
W
P
7
W
P
6
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
S
T
A
R
T
device type
identifier
device
addresses
S
A
C
K
instruction
opcode
WCR
addresses
S
A
C
K
Data Byte
(sent by master on SDA)
S
A
C
K
S
T
O
P
0
1
0
1
A
3
A
2
A
1
A
0
1
0
1
0
0
0
P
1
P
0
W
P
7
W
P
6
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
S
T
A
R
T
device type
identifier
device
addresses
S
A
C
K
instruction
opcode
DR and WCR
addresses
S
A
C
K
Data Byte
(sent by slave on SDA)
M
A
C
K
S
T
O
P
0
1
0
1
A
3
A
2
A
1
A
0
1
0
1
1
R
1
R
0
P
1
P
0
W
P
7
W
P
6
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
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