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參數(shù)資料
| 型號： | X9252UV24I-2.7 |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | Quad Digitally-Controlled (XDCP) potentiometer |
| 中文描述： | 四數(shù)字控制（數(shù)字電位器）電位 |
| 文件頁數(shù)： | 15/21頁 |
| 文件大?。?/td> | 126K |
| 代理商： | X9252UV24I-2.7 |
15 of 21
REV 1.4.1 7/29/03
www.xicor.com
X9252
The registers are organized in five pages of four, with
one page consisting of the WCRi (i=0-3), a second
page containing the DRi0 (i=0-3), a third page contain-
ing the DRi1, and so forth. These pages can be written
to four bytes at at time. In this manner all four potenti-
ometer WCRs can be updated in a single serial write
(see “Page Write Operation” on page 17), as well as all
four registers of a given page in the DR array.
The unique feature of the X9252 device is that writing
or reading to a Data Register of a given DCP automati-
cally updates/moves the WCR of that DCP with the
content of the DR. In this manner data can be moved
from a particular DCP register to that DCP’s WCR just
by performing a 2-wire read operation. Simulta-
neously, that data byte can be utilized by the host.
Status Register Organization
The Status Register (SR) is used in read and write
operations to select the appropriate DCP register.
Before any DCP register can be accessed, the SR
must be set to the correct value. It is accessed by
setting the Address Byte to 07h (Write Slave Address,
followed by Byte Address 07h). The SR is volatile and
defaults to 00h on power up. It is an 8-bit register
containing three control bits in the 3 LSBs as follows:
Bits DRSel0 and DRSel1 determine which Data Regis-
ter of a DCP is selected in a given operation. NVEn-
able is used to select the volatile WCR if “0”, and one
of the nonvolatile DCP registers if “1”. Table 2 shows
this register organization. “Store” operations using the
Up/Down interface require that bits DRSel1 and
DRSel0 are set to “0”.
Table 2. Status Register Contents for WCR and DR
Selection for 2-Wire Interface
Note:
X means either 0 or 1, i = 0,1,2, or 3
DCP Addressing for 2-wire Interface
Once the register number has been selected by a 2-
wire instruction, then the DCP number is determined
by the Address Byte of the following instruction. Note
again that this enables a complete page write of the
DRs of all four potentiometers at once. The register
addresses accessible in the X9252 include:
Table 3. Addressing for 2-wire Interface Address
Byte
All other address bits in the Address Byte must be set
to “0” during 2-wire write operations and their value
should be ignored when read.
7
6
5
4
3
2
1
0
Reserved
DRSel1
DRSel0
NVEnable
Register Selected
WCRi
DRi0
DRi1
DRi2
DRi3
DRSel1
X
0
0
1
1
DRSel0
X
0
1
0
1
NVEnable
0
1
1
1
1
Address (hex)
0
1
2
3
4
5
6
7
Contents
DCP 0
DCP 1
DCP 2
DCP 3
Not Used
Not Used
Not Used
Status Register
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參數(shù)描述 |
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| X9252WAZ WAF | 制造商:Intersil Corporation 功能描述: |
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| X9252WS24IZ-2.7 | 制造商:Intersil Corporation 功能描述:DGTL POTENTIOMETER 256POS 10KOHM QUAD 24SOIC W - Rail/Tube |
| X9252WV24-2.7 | 功能描述:IC DCP QUAD 10K 256TAP 24-TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)字電位器 系列:XDCP™ 標(biāo)準(zhǔn)包裝:2,500 系列:XDCP™ 接片:256 電阻（歐姆）:100k 電路數(shù):1 溫度系數(shù):標(biāo)準(zhǔn)值 ±300 ppm/°C 存儲器類型:非易失 接口:I²C（設(shè)備位址） 電源電壓:2.7 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:14-TSSOP 包裝:帶卷 (TR) |
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