參數(shù)資料
型號: X9252US24I-2.7
廠商: INTERSIL CORP
元件分類: 數(shù)字電位計
英文描述: Low Power + Quad 256-Tap + 2-Wire Bus + Up/Down Interface
中文描述: QUAD 50K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO24
封裝: PLASTIC, SOIC-24
文件頁數(shù): 1/21頁
文件大?。?/td> 126K
代理商: X9252US24I-2.7
REV 1.4.1 7/29/03
1 of 21
www.xicor.com
Quad Digitally-Controlled (XDCP
TM
) Potentiometer
X9252
FEATURES
Quad solid state potentiometer
256 wiper tap points–0.4% resolution
2-wire serial interface for Write, Read, and
transfer operations of the potentiometer
Up/down interface for individual potentiometers
Wiper resistance: 40
typical
Non-volatile storage of wiper positions
Power On Recall. Loads saved wiper position on
Power-Up.
Standby current < 20μA Max
Maximum wiper current: 3mA
V
CC
: 2.7V to 5.5V operation
2.8k
,
10k
, 50k
,
100k
resistance
Endurance: 100, 000 data changes per bit per
register
100 yr. data retention
24-Lead TSSOP
version of total pot
DESCRIPTION
The X9252 integrates 4 digitally controlled potentio-
meters (XDCP) on a monolithic CMOS integrated
circuit.
The digitally controlled potentiometers are imple-
mented using 255 resistive elements in a series array.
Between each pair of elements are tap points con-
nected to wiper terminals through switches. The posi-
tion of each wiper on the array is controlled by the user
through the Up/Down (U/D) or 2-wire bus interface.
The wiper of each potentiometer has an associated
volatile Wiper Counter Register (WCR) and four non-
volatile Data Registers (DRs) that can be directly writ-
ten to and read by the user. The contents of the WCR
controls the position of the wiper on the resistor array
though the switches. At power-up, the device recalls
the contents of the default data registers DR00, DR10,
DR20, DR30, to the corresponding WCR.
Each DCP can be used as a three-terminal potentio-
meter or as a two terminal variable resistor in a wide
variety of applications including the programming of
bias voltages, the implementation of ladder networks,
and three resistor programmable networks.
Low Power + Quad 256-tap +
2-Wire bus + Up/Down interface
New Feature
Dual Interface
FUNCTIONAL DIAGRAM
POWER UP,
INTERFACE
CONTROL
AND
STATUS
V
CC
V
SS
2-Wire
Interface
R
H0
R
L0
DCP0
R
W0
A1
SDA
SCL
CS
U/D
A2
DS0
DS1
WP
WCR0
DR00
DR01
DR02
DR03
R
H1
R
L1
DCP1
R
W1
WCR1
DR10
DR11
DR12
DR13
R
H2
R
L2
DCP2
R
W2
WCR2
DR20
DR21
DR22
DR23
R
H3
R
L3
DCP3
R
W3
WCR3
DR30
DR31
DR32
DR33
A0
Up-Down
Interface
相關(guān)PDF資料
PDF描述
X9252US24IZ-2.7 Low Power + Quad 256-Tap + 2-Wire Bus + Up/Down Interface
X9252WS24I-2.7 RES ARRAY 10 OHM 8TERM 4RES SMD
X9252YV24IZ-2.7 Low Power + Quad 256-Tap + 2-Wire Bus + Up/Down Interface
X9252WV24IZ-2.7 KIT RF SHIELD LARGE MULTI-HEIGHT
X9252UV24IZ-2.7 KIT RF SHIELD SMALL MULTI-HEIGHT
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