- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372539 > X9250UZ24 DIGITAL POTENTIOMETER|CMOS|BGA|24PIN|PLASTIC PDF資料下載
參數(shù)資料
| 型號： | X9250UZ24 |
| 元件分類： | 數(shù)字電位計 |
| 英文描述： | DIGITAL POTENTIOMETER|CMOS|BGA|24PIN|PLASTIC |
| 中文描述： | 數(shù)字電位器|的CMOS | BGA封裝| 24針|塑料 |
| 文件頁數(shù)： | 2/21頁 |
| 文件大?。?/td> | 181K |
| 代理商： | X9250UZ24 |
X9250
Characteristics subject to change without notice.
2 of 21
REV 1.1.5 1/31/03
www.xicor.com
PIN DESCRIPTIONS
Serial Output (SO)
SO is a serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by
the falling edge of the serial clock.
Serial Input
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9250.
Chip Select (CS)
When CS is HIGH, the X9250 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9250, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.
Device Address (A
The address inputs are used to set the least significant
2 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9250. A maximum of 4 devices may occupy the
SPI serial bus.
0
–
A
1
)
Potentiometer Pins
V
H
/R
H
(V
H0
/R
H0
–V
H3
/R
H3
), V
L
/R
L
(V
L0
/R
L0
–V
L3
/R
L3
)
The R
connections on a mechanical potentiometer.
H
and R
L
pins are equivalent to the terminal
V
W
/R
W
(V
W0
/R
W0
–V
W3
/R
W3
)
The wiper pins are equivalent to the wiper terminal of
a mechanical potentiometer.
Hardware Write Protect Input (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
Analog Supplies (V+, V-)
The analog supplies V+, V- are the supply voltages for
the XDCP analog section.
PIN CONFIGURATION
S0
A0
V
W3
/R
W3
V
H3
/R
H3
V
L3
/R
L3
V+
V
CC
V
L0
/R
L0
V
H0
/R
H0
V
W0
/R
W0
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
15
HOLD
SCK
V
L2
/R
L2
V
H2
/R
L2
V
W2
/R
W2
V–
V
SS
V
W1
/R
W1
V
H1
/R
H1
V
L1
/R
L1
SOIC/TSSOP
X9250
14
13
11
12
CS
A1
SI
WP
2
3
4
1
A
B
C
D
E
F
Top View–Bumps Down
R
W0
R
L0
V+
A
0
HOLD
R
L1
V
CC
R
L3
R
W3
SO
SI
R
W1
SCK R
L2
WP
V-
R
H0
R
H1
R
H3
R
H2
V
SS
R
W2
CS
A
1
CSP
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X9250UZ24-2.7 | DIGITAL POTENTIOMETER|CMOS|BGA|24PIN|PLASTIC |
| X9250TS24-2.7 | Quad Digitally Controlled Potentiometers (XDCP) |
| X9250TS24I | Quad Digitally Controlled Potentiometers (XDCP) |
| X9250TS24I-2.7 | Quad Digitally Controlled Potentiometers (XDCP) |
| X9250TV24 | Quad Digitally Controlled Potentiometers (XDCP) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X9250UZ24-2.7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DIGITAL POTENTIOMETER|CMOS|BGA|24PIN|PLASTIC |
| X9250UZ24I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DIGITAL POTENTIOMETER|CMOS|BGA|24PIN|PLASTIC |
| X9250UZ24I-2.7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DIGITAL POTENTIOMETER|CMOS|BGA|24PIN|PLASTIC |
| X9251 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Single Supply/Low Power/256-Tap/SPI Bus |
| X9251_07 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Quad Digitally-Controlled (XDCP⑩) Potentiometer |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。