參數(shù)資料
型號(hào)： X9250
廠商： Intersil Corporation
英文描述： Low Noise/Low Power/SPI Bus/256 Taps
中文描述： 低噪音/低功耗/水龍頭的SPI Bus/256
文件頁(yè)數(shù)： 4/21頁(yè)
文件大?。?/td> 181K
代理商： X9250
X9250
Characteristics subject to change without notice.
4 of 21
REV 1.1.5 1/31/03
www.xicor.com
Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW
to HIGH after a complete write sequence is received
by the device. The progress of this internal write
operation can be monitored by a write in process bit
(WIP). The WIP bit is read with a read status
command.
INSTRUCTIONS
Identification (ID) Byte
The first byte sent to the X9250 from the host,
following a CS going HIGH to LOW, is called the
Identification byte. The most significant four bits of the
slave address are a device type identifier, for the
X9250 this is fixed as 0101[B] (refer to Figure 2).
The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
address is defined by the state of the A
0
-A
1
input pins.
The X9250 compares the serial data stream with the
address input state; a successful compare of both
address bits is required for the X9250 to successfully
continue the command sequence. The A
0
–A
1
inputs
can be actively driven by CMOS input signals or tied to
V
CC
or V
SS
.
The remaining two bits in the slave byte must be set to 0.
Figure 2. Identification Byte Format
Instruction Byte
The next byte sent to the X9250 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next four
bits point to one of the four pots and, when applicable,
they point to one of four associated registers. The
format is shown below in Figure 3.
Figure 3. Instruction Byte Format
1
0
0
0
0
A1
A0
Device Type
Identifier
Device Address
1
I1
I2
I3
I0
R1
R0
P1
P0
Pot Select
Register
Select
Instructions
Figure 1. Detailed Potentiometer Block Diagram
Serial Data Path
From Interface
Circuitry
Register 0
Register 1
Register 2
Register 3
Serial
Bus
Input
Parallel
Bus
Input
Counter
Register
(WCR)
Inc/Dec
Logic
UP/DN
CLK
Modified SCK
UP/DN
V
H
/R
H
V
L
/R
L
V
W
/R
W
8
8
C
o
u
n
t
e
r
D
e
c
o
d
e
If WCR = 00[H] then V
W
/R
W
= V
L
/R
L
If
WCR = FF[H]
then
V
W
/R
W
= V
H
/R
H
Wiper
(One of Four Arrays)
相關(guān)PDF資料
PDF描述
X9250-2.7 Low Noise/Low Power/SPI Bus/256 Taps
X9250UV24I-2.7 Low Noise/Low Power/SPI Bus/256 Taps
X9250TS24 Low Noise/Low Power/SPI Bus/256 Taps
X9250TS24-2.7 Low Noise/Low Power/SPI Bus/256 Taps
X9250TS24I Low Noise/Low Power/SPI Bus/256 Taps
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
X9250_06 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Quad Digitally Controlled Potentiometers
X9250-2.7 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low Noise/Low Power/SPI Bus/256 Taps
X9250TB24 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Quad Digitally Controlled Potentiometers (XDCP)
X9250TB24-2.7 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Quad Digitally Controlled Potentiometers (XDCP)
X9250TB24I 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Quad Digitally Controlled Potentiometers (XDCP)
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