RW The wiper pin are equivalent to the wiper terminal of a mechanical potentiom" />
參數(shù)資料
型號(hào)： X9119TV14
廠(chǎng)商： Intersil
文件頁(yè)數(shù)： 12/17頁(yè)
文件大?。?/td> 0K
描述： IC DCP 100K 1024TP 14TSSOP
標(biāo)準(zhǔn)包裝： 95
系列： XDCP™
接片： 1024
電阻（歐姆）： 100k
電路數(shù)： 1
溫度系數(shù)： 標(biāo)準(zhǔn)值 ±300 ppm/°C
存儲(chǔ)器類(lèi)型： 非易失
接口： I²C（設(shè)備位址）
電源電壓： 4.5 V ~ 5.5 V
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 14-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 14-TSSOP
包裝： 管件
4
FN8162.4
July 9, 2008
RW
The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer.
Bias Supply Pins
SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY
GROUND (VSS)
The VCC pin is the system supply voltage. The VSS pin is
the system ground.
Other Pins
NO CONNECT
No connect pins should be left open. These pins are used for
Intersil manufacturing and testing purposes.
Principals of Operation
The X9119 is an integrated microcircuit incorporating a
resistor array and its associated registers and counters and
the serial interface logic providing direct communication
between the host and the digitally controlled potentiometer.
This section provides detail description of the following:
Resistor Array Description
Serial Interface Description
Instruction and Register Description
Resistor Array Description
The X9119 is comprised of a resistor array. The array
contains, in effect, 1023 discrete resistive segments that are
connected in series (Figure 1). The physical ends of each
array are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper (RW)
output. Within each individual array only one switch may be
turned on at a time. These switches are controlled by the
Wiper Counter Register (WCR). The 10-bits of the WCR
(WCR[9:0]) are decoded to select, and enable, one of 1024
switches.
The WCR may be written directly. The Data Registers and
the WCR can be read and written by the host system.
Serial Interface Description
SERIAL INTERFACE
The X9119 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master will always
initiate data transfers and provide the clock for both transmit
and receive operations. Therefore, the X9119 will be
considered a slave device in all applications.
CLOCK AND DATA CONVENTIONS
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions (Figure 3).
START CONDITION
All commands to the X9119 are preceded by the start
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The X9119 continuously monitors the SDA
and SCL lines for the start condition and will not respond to
any command until this condition is met (Figure 3).
SERIAL DATA PATH
FROM INTERFACE
REGISTER 0
SERIAL
BUS
INPUT
PARALLEL
BUS
INPUT
COUNTER
REGISTER
R H
R L
R
W
10
C
O
U
N
T
E
R
D
E
C
O
D
E
IF WCR = 000[HEX] THEN RW = RL
IF WCR = 3FF[HEX] THEN RW = RH
WIPER
(WCR)
(DR0)
CIRCUITRY
REGISTER 1
(DR1)
REGISTER 2
(DR2)
REGISTER 3
(DR3)
FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM SERIAL INTERFACE DESCRIPTION
R
X9119
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