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參數資料
| 型號： | X9118TV14-2.7 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 數字電位計 |
| 英文描述： | Dual Suply/Low Power/1024-Tap/2-Wire Bus |
| 中文描述： | 100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 1024 POSITIONS, PDSO14 |
| 封裝： | PLASTIC, MO-153AC, TSSOP-14 |
| 文件頁數： | 4/20頁 |
| 文件大?。?/td> | 348K |
| 代理商： | X9118TV14-2.7 |
4
FN8161.1
March 25, 2005
PRINCIPLES OF OPERATION
The X9118 is an integrated microcircuit incorporating
a resistor array and their its registers and counters and
the serial interface logic providing direct
communication between the host and the digitally
controlled potentiometer. This section provides detail
description of the following:
– Resistor Array Description
– Serial Interface Description
– Instruction and Register Description
Resistor Array Description
The X9118 is comprised of a resistor array. The array
contains 1023, in effect, discrete resistive segments
that are connected in series (see Figure 1). The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (R
H
and R
L
inputs).
At both ends of each array and between each resistor
segment is a CMOS switch (transmission gate)
connected to the wiper (R
W
) output. Within each
individual array only one switch may be turned on at a
time. These switches are controlled by the Wiper
Counter Register (WCR). The 10-bits of the WCR
(WCR[9:0]) are decoded to select, and enable, one of
1024 switches.
The WCR may be written directly. The Data Registers
and the WCR can be read and written by the host
system.
Figure 1. Detailed Potentiometer Block Diagram
Serial Interface Description
S
ERIAL
I
NTERFACE
– 2-W
IRE
The X9118 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9118 will be considered a
slave device in all applications.
C
LOCK
AND
D
ATA
C
ONVENTIONS
Data states on the SDA line can change only during
SCL LOW periods. SDA state changes during SCL
HIGH are reserved for indicating start and stop
conditions. See Figure 3.
S
TART
C
ONDITION
All commands to the X9118 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH. The X9118 continuously monitors
the SDA and SCL lines for the start condition and will
not respond to any command until this condition is
met. See Figure 3.
Serial Data Path
From Interface
Circuitry
Register 0
(DR0)
Serial
Bus
Input
Parallel
Bus
Input
Counter
Register
(WCR)
RH
RL
RW
10
10
C
O
U
N
T
E
R
D
E
C
O
D
E
If WCR = 000[HEX] then R
W
= R
L
If
WCR = 3FF[HEX]
then
R
W
=
R
H
Wiper
Register 1
(DR1)
Register 2
(DR2)
Register 3
(DR3)
X9118
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