參數(shù)資料
型號(hào): X9118-2.7
廠(chǎng)商: Intersil Corporation
英文描述: Dual Suply/Low Power/1024-Tap/2-Wire Bus
中文描述: 雙敘普利/低Power/1024-Tap/2-Wire巴士
文件頁(yè)數(shù): 6/20頁(yè)
文件大?。?/td> 348K
代理商: X9118-2.7
6
FN8161.1
March 25, 2005
FLOW 1. ACK Polling Sequence
I
NSTRUCTION
AND
R
EGISTER
D
ESCRIPTION
D
EVICE
A
DDRESSING
: I
DENTIFICATION
B
YTE
(ID
AND
A)
Following a start condition the master must output the
address of the slave it is accessing. The most
significant four bits of the slave address are the device
type identifier. The ID[3:0] bits is the device id for the
X9118; this is fixed as 0101[B] (refer to Table 1).
The A[1:0] bits in the ID byte are the internal slave
address. The physical device address is defined by the
state of the A1-A0 input pins. The slave address is
externally specified by the user. The X9118 compares
the serial data stream with the address input state; a
successful compare of both address bits is required for
the X9118 to successfully continue the command
sequence. Only the device which slave address
matches the incoming device address sent by the
master executes the instruction. The A1-A0 inputs can
Instruction and Register Description
be actively driven by CMOS input signals or tied to
V
CC
or V
SS
. The R/W bit is the LSB and is used to set
the device for read or write operations.
I
NSTRUCTION
B
YTE
AND
R
EGISTER
S
ELECTION
The next byte sent to the X9118 contains the
instruction and register pointer information. The three
most significant bits are used provide the instruction
opcode (I[2:0]). The RB and RA bits point to one of the
four registers. The format is shown below in Table 2.
Table 3 provides a complete summary of the
instruction set opcodes.
Table 1. Identification Byte Format
Table 2. Instruction Byte Format
Nonvolatile Write
Command Completed
EnterACK Polling
Issue
START
Issue Slave
Address
ACK
Returned
Further
Operation
Issue
Instruction
Issue STOP
No
Yes
Yes
Proceed
Issue STOP
No
Proceed
ID3
ID2
ID1
ID0
0
0
A0
R/W
0
1
0
1
(MSB)
(LSB)
Device Type
Identifies
Set to 0
for Proper
Operation
Internal Slave
Address
Read or
Write Bit
I2
I1
I0
0
RB
RA
0
0
(MSB)
(LSB)
Instruction
Opcode
Set to 0
for Proper
Operation
Register
Selection
Set to 0 for
Proper Operation
X9118
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