- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376445 > X80204V20I (INTERSIL CORP) Power Supply Swquencer with Power-up System Mnitoring PDF資料下載
參數(shù)資料
| 型號(hào)： | X80204V20I |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | Power Supply Swquencer with Power-up System Mnitoring |
| 中文描述： | 3-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO20 |
| 封裝： | PLASTIC, TSSOP-20 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 332K |
| 代理商： | X80204V20I |
12
FN8154.0
Read Operation
A Read operation is initiated in the same manner as a write
operation with the exception that the R/W bit of the Slave
Address Byte is set to one.
Prior to issuing the Slave Address Byte with the R/W bit set to
one, the master must first perform a “dummy” write operation.
The master issues the start condition and the Slave Address
Byte, receives an acknowledge, then issues the Word Address
Byte. After acknowledging receipt of the Word Address Byte,
the master immediately issues another start condition and the
Slave Address Byte with the R/W bit set to one. This is followed
by an acknowledge from the device and then by the data byte
containing the register contents. The master terminates the
read operation by responding with a no-acknowledge and then
issuing a stop condition. The ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read operation,
the master must either issue a stop condition during the
ninth cycle or hold SDA HIGH during the ninth clock cycle
and then issue a stop condition.
See Figure 12 for the address, acknowledge, and data
transfer sequence. See Figure 1 for bus timing.
Operational Notes
The device powers-up in the following state:
The device is in the low power standby state.
The WEL bit is set to ‘0’. It is not possible to write to the
device.
The WEL bit must be set to allow write operations.
SDA pin is the input mode.
The data in the RSR powers up in ‘0’ state.
SA6
SA7
SA5
SA2
SA1
SA0
DEVICE TYPE
IDENTIFIER
READ/
WRITE
SA4
R/W
1
0
1
0
ADDRESS
INTERNAL
DEVICE
A2
A1
A0
BIT SA0
OPERATION
0
WRITE
1
READ
BA7
BA6
BA5
BA4
BA3
BA2
BA1
BA0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D7
DATA BYTE
D6
D5
D4
D3
D2
D1
D0
SLAVE ADDRESS
SR
RSR
SA3
WORD ADDRESS
0
1
FIGURE 10. ADDRESS FORMAT
X80200, X80201, X80202, X80203, X80204
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X80200 | Power Supply Swquencer with Power-up System Mnitoring |
| X80200V20I | Power Supply Swquencer with Power-up System Mnitoring |
| X80201 | Power Supply Swquencer with Power-up System Mnitoring |
| X80202 | Power Supply Swquencer with Power-up System Mnitoring |
| X80203 | Power Supply Swquencer with Power-up System Mnitoring |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X8037QC | 制造商:ABRACON 制造商全稱:Abracon Corporation 功能描述:38-640MHz Low Phase Noise XO |
| X8037QCL | 制造商:ABRACON 制造商全稱:Abracon Corporation 功能描述:38-640MHz Low Phase Noise XO |
| X80386DX WAF | 制造商:Intel 功能描述: |
| X80386EX WAF | 制造商:Intel 功能描述: |
| X80386SX WAF | 制造商:Intel 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。