- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376445 > X80203 (Intersil Corporation) Power Supply Swquencer with Power-up System Mnitoring PDF資料下載
參數(shù)資料
| 型號： | X80203 |
| 廠商： | Intersil Corporation |
| 英文描述： | Power Supply Swquencer with Power-up System Mnitoring |
| 中文描述： | 電源Swquencer與上電系統(tǒng)Mnitoring， |
| 文件頁數(shù)： | 8/16頁 |
| 文件大小： | 332K |
| 代理商： | X80203 |
8
FN8154.0
The READY output pin reflects the condition of the VDDH
input. READY is LOW as long as VDDH is below UVLO
H
and remains LOW for a period of t
PURST
after VDDH
crosses UVLO
H
, see Figure 4. Once VDDH rises above
UVLO
H
and remains stable for t
PURST
, the READY output
turns ON. If READY connects directly to the GATEH_EN pin,
then the GATE_H charge pump turns on immediately. The
turn on of the Gate_H charge pump can be delayed by using
an external filter (RC filter) connected between the READY
and GATEH_EN pins.
When VDDH drops below the UVLO
H
threshold, READY
goes inactive immediately. For more details on this turn-off
mechanism, See "Power Supply Failure Conditions" on
page 9.
SECONDARY VOLTAGES VDDM AND VDDL
The VDDM and VDDL voltage inputs each have their own
undervoltage lockout settings, UVLO
M
, and UVLO
L
,
respectively. Each undervoltage lockout level is preset at the
factory. For information on these settings, See Ordering
Information. For custom programmed levels, contact Intersil.
The GATE_M and GATE_ L charge pumps are OFF as long
as VDDM, and VDDL are below their respective UVLO trip
points. When READY is active and VDDM and VDDL go
above their UVLO thresholds, the GATE_M and GATE_L
charge pumps can be turned ON when activated as part of
the power sequence desired. If VDDL or VDDM drop below
the UVLO level the charge pumps turn off. For more details
on this turn-off mechanism, See "Power Supply Failure
Conditions" on page 9.
Sequence Delay Logic.
This block contains the logic
circuits that implement the power-up and power-down
sequencing of the VDDH (GATE_H), VDDM (GATE_M), and
VDDL (GATE_L) voltages. The sequencing protocol has a
built-in “core-first-up and core-down-last” algorithm. On
power-up the GATE_L signal turns on first, followed by
GATE_M signal. During the power-down, the GATE_M turns
off first and the GATE_L signal follows.
The sequencing of the power supplies is primarily controlled
and regulated via the SETV and the ENS (enable sequence)
pins.
All charge pumps are designed to ramp up their respective
gates at the same slew rate for the same load.
Time Based Power Sequencing (ENS option)
The ENS (Enable Sequence) pin controls the start of the
ramp up/ramp down sequence for GATE_M and GATE_L in
the time domain. (See Figure 3.)
ENS is an edge-triggered input. A rising edge (LOW to
HIGH) on the ENS input turns on the charge pump that
drives the GATE_L output. The slew rate of the GATE_L
output depends on the external MOSFET and any load
connected to it. (See Electrical Table). After a t
DELAY_UP
time, the GATE_M charge pump turns ON. Again the slew
rate is dependent on the load connected to GATE_M output.
The falling edge transition on the ENS pin (HIGH to LOW)
turns off the charge pump that drives the GATE_M output.
After a t
DELAY_DOWN
time period, the GATE_L charge
pump turns OFF.
Voltage Based Power Sequencing (SETV Option)
Using the SETV pin allows for a voltage based sequencing
of the GATE_L and GATE_M outputs. SETV is an edge
triggered input signal. A LOW to HIGH transition on SETV
immediately turns ON the charge pump for GATE_L. The
GATE_L output then starts ramping up. In this configuration,
the drain of the MOSFET “L” connects to the VFB pin and
this voltage is compared to an external reference applied to
the REF pin. The comparator turns on the charge pump for
GATE_M once the voltage on VFB exceeds the voltage on
REF. (See Figure 5.)
The voltage sequencing comparator has a 30mV hysteresis,
so the GATE_M output does not oscillate as the core voltage
powers up.
A High to Low transition of SETV turns OFF charge pump M
and GATE_M is pulled low. After a t
DELAY_DOWN
time
period, charge pump L turns off and GATE_L is pulled low.
t
DELAY_UP
ENS
GATE_L
GATE_M
t
DELAY_DOWN
FIGURE 3. TIME BASED SEQUENCING OF GATE_M AND
GATE_L
t
PURST
UVLO
H
VDDH
READY
FIGURE 4. VDDH/READY SEQUENCING
X80200, X80201, X80202, X80203, X80204
相關PDF資料 |
PDF描述 |
|---|---|
| X80204 | Power Supply Swquencer with Power-up System Mnitoring |
| X80201V20I | Power Supply Swquencer with Power-up System Mnitoring |
| X9015WS8T1 | Single Digitally Controlled Potentiometer |
| X9015WS8ZT1 | Single Digitally Controlled Potentiometer |
| X9111TV14IZ | Single Digitally-Controlled (XDCP⑩) Potentiometer |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| X80203V20I | 功能描述:IC PWR SUPPLY SEQUENCER 20TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 電源控制器，監(jiān)視器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 應用:多相控制器 輸入電壓:- 電源電壓:9 V ~ 14 V 電流 - 電源:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應商設備封裝:40-TQFN-EP（5x5） 包裝:帶卷 (TR) |
| X80204 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Power Supply Swquencer with Power-up System Mnitoring |
| X80204V20I | 功能描述:IC PWR SUPPLY SEQUENCER 20TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 電源控制器，監(jiān)視器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 應用:多相控制器 輸入電壓:- 電源電壓:9 V ~ 14 V 電流 - 電源:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應商設備封裝:40-TQFN-EP（5x5） 包裝:帶卷 (TR) |
| X8037QC | 制造商:ABRACON 制造商全稱:Abracon Corporation 功能描述:38-640MHz Low Phase Noise XO |
| X8037QCL | 制造商:ABRACON 制造商全稱:Abracon Corporation 功能描述:38-640MHz Low Phase Noise XO |
發(fā)布緊急采購，3分鐘左右您將得到回復。