參數(shù)資料
型號(hào): X80200
廠商: Intersil Corporation
英文描述: Power Supply Swquencer with Power-up System Mnitoring
中文描述: 電源Swquencer與上電系統(tǒng)Mnitoring,
文件頁(yè)數(shù): 6/16頁(yè)
文件大?。?/td> 332K
代理商: X80200
6
FN8154.0
Timing Diagrams
Bus Interface AC Timing
SYMBOL
PARAMETER
TEST
CONDITION
SMBUS
2-WIRE BUS
UNITS
MIN
MAX
MIN
MAX
f
SCL
Clock Frequency
10
100
400
kHz
t
CYC
Clock Cycle Time
10
2.5
μs
t
HIGH
Clock High Time
4.0
50
0.6
μs
t
LOW
Clock Low Time
4.7
1.3
μs
t
SU:STA
Start Set-up Time
4.7
0.6
μs
t
HD:STA
Start Hold Time
4.0
0.6
μs
t
SU:STO
Stop Set-up Time
4.0
0.6
μs
t
SU:DAT
SDA Data Input Set-up Time
250
100
ns
t
HD:DAT
SDA Data Hold Time
300
0
ns
t
R
SCL and SDA Rise Time: TR = (V
ILMAX
- 0.15) to
(V
IHMIN
+0.15)
(Note 1)
1000
300
ns
t
F
SCL and SDA Fall Time: TF = (V
IHMIN
- 0.15) to
(V
ILMAX
- 0.15)
(Note 1)
300
300
ns
t
AA
SCL Low to SDA Data Output Valid Time
(Note 1)
550
1100
250
1100
ns
t
DH
SDA Data Output Hold Time
(Note 1)
300
0
ns
T
I
Noise Suppression Time Constant at SCL and SDA inputs
(Note 1)
50
50
ns
t
BUF
Bus Free Time (Prior to Any Transmission)
(Note 1)
4.7
1.3
μs
t
SU:A
A0, A1, A2 Set-up Time
0
0
ns
t
HD:A
A0, A1, A2 Hold Time
0
0
ns
FIGURE 1. BUS TIMING
t
SU:STO
t
HIGH
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
SCL
SDA IN
SDA OUT
t
F
t
LOW
t
HD:DAT
t
R
t
DH
t
AA
t
BUF
t
HD:STO
t
BUF
t
HD:A
SCL
SDA IN
A2, A1, A0
t
SU:A
CLK 1
CLK 9
SLAVE ADDRESS BYTE
START
FIGURE 2. ADDRESS PIN TIMING
X80200, X80201, X80202, X80203, X80204
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