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參數(shù)資料
| 型號(hào)： | X76F100P |
| 英文描述： | 1K 128 x 8 Bit |
| 中文描述： | 每1000 128 × 8位 |
| 文件頁數(shù)： | 3/17頁 |
| 文件大小： | 275K |
| 代理商： | X76F100P |
X76F100
Characteristics subject to change without notice.
3 of 16
REV 1.0 6/22/00
www.xicor.com
After each transaction is completed, the X76F100 will
reset and enter into a standby mode. This will also be
the response if an unsuccessful attempt is made to
access a protected array.
Figure 1. X76F100 Device Operation
Retry Counter
The X76F100 contains a retry counter. The retry
counter allows 8 accesses with an invalid password
before any action is taken. The counter will increment
with any combination of incorrect passwords. If the
retry counter overflows, the memory area and both of
the passwords are cleared to “0”. If a correct password
is received prior to retry counter overflow, the retry
counter is reset and access is granted.
Device Protocol
The X76F100 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as a receiver. The device controlling the transfer
is a master and the device being controlled is the
slave. The master will always initiate data transfers and
provide the clock for both transmit and receive opera-
tions. Therefore, the X76F100 will be considered a
slave in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figure 2 and Figure 3.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X76F100 continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition is met.
A start may be issued to terminate the input of a con-
trol byte or the input data to be written. This will reset
the device and leave it ready to begin a new read or
write command. Because of the push/pull output, a
start cannot be generated while the part is outputting
data. Starts are inhibited while a write is in progress.
Stop Condition
All communications must be terminated by a stop con-
dition. The stop condition is a LOW to HIGH transition
of SDA when SCL is HIGH. The stop condition is also
used to reset the device during a command or data
input sequence and will leave the device in the standby
power mode. As with starts, stops are inhibited when
outputting data and while a write is in progress.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data.
The X76F100 will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a write condition have been
selected, the X76F100 will respond with an acknowl-
edge after the receipt of each subsequent eight-bit
word.
Load Command/Address Byte
Load 8-Byte
Password
Verify Password
Acceptance by
Use of Ack Polling
Read/Write
Data
Bytes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X76F100P-3.0 | 1K 128 x 8 Bit |
| X76F100PI | 1K 128 x 8 Bit |
| X76F100PI-3.0 | 1K 128 x 8 Bit |
| X76F100S8 | 1K 128 x 8 Bit |
| X76F100S8-3.0 | 1K 128 x 8 Bit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X76F100P-3.0 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:1K 128 x 8 Bit |
| X76F100PI | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:1K 128 x 8 Bit |
| X76F100PI-3.0 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:1K 128 x 8 Bit |
| X76F100S8 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:1K 128 x 8 Bit |
| X76F100S8-3.0 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:1K 128 x 8 Bit |
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