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參數(shù)資料
| 型號(hào)： | X68C64P |
| 英文描述： | E2 Micro-Peripheral |
| 中文描述： | E2微型外設(shè) |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 62K |
| 代理商： | X68C64P |
X68C64
5
cycle is complete, the toggling will cease and the device
will be accessible for additional read or write operations.
Due to the dual plane architecture, reads for polling must
occur in the plane that is being written; that is, the state
of A
12
during a write must match the state of A
12
during
Toggle Bit Polling.
Toggle Bit Polling
Because the X68C64 typical nonvolatile write cycle time
is less than the specified 5ms, Toggle Bit Polling has
been provided to determine the early completion of
write. During the internal programming cycle, I/O
6
will
toggle from HIGH to LOW and LOW to HIGH on subse-
quent attempts to read the device. When the internal
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Changing:
State Not
Known
Center Line
is High
Impedance
Toggle Bit Polling E Control
3868 FHD F08
CE
AS
A/D0–A/D7
A8–A12
E
R/W
AIN
DIN
A12=n
OPERATION
LAST BYTE
WRITTEN
I/O6=X
X68C64 READY FOR
NEXT OPERATION
AIN
DOUT
A12=n
AIN
DOUT
A12=n
AIN
DOUT
A12=n
AIN
A12=n
AIN
ADDR
I/O6=X
I/O6=X
I/O6=X
DOUT
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X68C64PI | E2 Micro-Peripheral |
| X68C64PM | E2 Micro-Peripheral |
| X68C64S | E2 Micro-Peripheral |
| X68C64SI | E2 Micro-Peripheral |
| X68C64SM | E2 Micro-Peripheral |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X68C64PI | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:E2 Micro-Peripheral |
| X68C64PM | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:E2 Micro-Peripheral |
| X68C64S | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:E2 Micro-Peripheral |
| X68C64SI | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:E2 Micro-Peripheral |
| X68C64SM | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:E2 Micro-Peripheral |
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