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參數(shù)資料
| 型號： | X5328V14I |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO14 |
| 封裝： | PLASTIC, TSSOP-14 |
| 文件頁數(shù)： | 17/21頁 |
| 文件大?。?/td> | 388K |
| 代理商： | X5328V14I |
X5328/X5329
Characteristics subject to change without notice.
5 of 21
REV 1.1.3 11/13/02
www.xicor.com
SPI SERIAL MEMORY
The memory portion of the device is a CMOS Serial
EEPROM array with Xicor’s block lock protection. The
array is internally organized as x 8. The device features
a Serial Peripheral Interface (SPI) and software proto-
col allowing operation on a simple four-wire bus.
The device utilizes Xicor’s proprietary Direct Write
cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families. It contains an 8-bit
instruction register that is accessed via the SI input,
with data being clocked in on the rising edge of SCK.
CS must be LOW during the entire operation.
All instructions (Table 1), addresses and data are trans-
ferred MSB rst. Data input on the SI line is latched on
the rst rising edge of SCK after CS goes LOW. Data is
output on the SO line by the falling edge of SCK. SCK
is static, allowing the user to stop the clock and then
start it again to resume operations where left off.
Write Enable Latch
The device contains a Write Enable Latch. This latch
must be SET before a Write Operation is initiated. The
WREN instruction will set the latch and the WRDI
instruction will reset the latch (Figure 3). This latch is
automatically reset upon a power-up condition and
after the completion of a valid Write Cycle.
Status Register
The RDSR instruction provides access to the Status
Register. The Status Register may be read at any time,
even during a Write Cycle. The Status Register is for-
matted as follows:
*Bits (5,4) should be written as ‘1’ only.
The Write-In-Progress (WIP) bit is a volatile, read only
bit and indicates whether the device is busy with an
internal nonvolatile write operation. The WIP bit is read
using the RDSR instruction. When set to a “1”, a non-
volatile write operation is in progress. When set to a “0”,
no write is in progress.
7
6
543
2
1
0
WPEN
FLB
1*
BL1
BL0
WEL
WIP
Table 1. Instruction Set
Note:
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB rst.
Table 2. Block Protect Matrix
Instruction Name
Instruction Format*
Operation
WREN
0000 0110
Set the Write Enable Latch (Enable Write Operations)
SFLB
0000 0000
Set Flag Bit
WRDI/RFLB
0000 0100
Reset the Write Enable Latch/Reset Flag Bit
RSDR
0000 0101
Read Status Register
WRSR
0000 0001
Write Status Register (Block Lock, WPEN & Flag Bits)
READ
0000 0011
Read Data from Memory Array Beginning at Selected Address
WRITE
0000 0010
Write Data to Memory Array Beginning at Selected Address
WREN CMD
Status Register
Device Pin
Block
Status Register
WEL
WPEN
WP#
Protected Block
Unprotected Block
WPEN, BL0, BL1,
WD0, WD1
0
X
Protected
1
0
Protected
Writable
Protected
1
0
X
Protected
Writable
1
X
1
Protected
Writable
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