參數(shù)資料
型號: X5323V14
元件分類: 電源管理
英文描述: 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14
封裝: PLASTIC, TSSOP-14
文件頁數(shù): 18/21頁
文件大小: 200K
代理商: X5323V14
X5323/X5325
Characteristics subject to change without notice.
6 of 21
REV 1.1.2 11/13/01
www.xicor.com
Table 2. Block Protect Matrix
WREN CMD
Status Register
Device Pin
Block
Status Register
WEL
WPEN
WP#
Protected Block
Unprotected Block
WPEN, BL0, BL1
WD0, WD1
0
X
Protected
1
0
Protected
Writable
Protected
1
0
X
Protected
Writable
1
X
1
Protected
Writable
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch. When WEL = 1, the latch is
set HIGH and when WEL = 0 the latch is reset LOW.
The WEL bit is a volatile, read only bit. It can be set by
the WREN instruction and can be reset by the WRDS
instruction.
The block lock bits, BL0 and BL1, set the level of block
lock protection. These nonvolatile bits are programmed
using the WRSR instruction and allow the user to protect
one quarter, one half, all or none of the EEPROM array.
Any portion of the array that is block lock protected can be
read but not written. It will remain protected until the BL
bits are altered to disable block lock protection of that
portion of memory.
The watchdog timer bits, WD0 and WD1, select the
watchdog time out period. These nonvolatile bits are
programmed with the WRSR instruction.
The FLAG bit shows the status of a volatile latch that
can be set and reset by the system using the SFLB
and RFLB instructions. The ag bit is automatically
reset upon power up. This ag can be used by the sys-
tem to determine whether a reset occurs as a result of
a watchdog time out or power failure.
Notes: 1.
The Watch Dog Timer is shipped disabled. (WD1 = 1,
WD0 = 1)
2.
The factory default for Memory Block Protection is
‘None’. (BL1 = 0), BL0 = 0)
The nonvolatile WPEN bit is programmed using the
WRSR instruction. This bit works in conjunction with the
WP pin to provide an in-circuit programmable ROM func-
tion (Table 2). WP is LOW and WPEN bit programmed
HIGH disables all status register write operations.
In Circuit Programmable ROM Mode
This mechanism protects the block lock and watchdog
bits from inadvertent corruption.
In the locked state (
programmable ROM mode) the WP
pin is LOW and the nonvolatile bit WPEN is “1”. This
mode disables nonvolatile writes to the device’s status
register.
Status
Register Bits
Array Addresses Protected
BL1
BL0
X5323/X5325
0
None (factory default)
0
1
$0C00–$0FFF
1
0
$0800–$0FFF
1
$0000–$0FFF
Status Register Bits
Watchdog Time Out
(Typical)
WD1
WD0
0
1.4 seconds
0
1
600 milliseconds
1
0
200 milliseconds
1
disabled (factory default)
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