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參數(shù)資料
| 型號： | X5168S8I-4.5A-T1 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8 |
| 封裝： | PLASTIC, SOIC-8 |
| 文件頁數(shù)： | 16/19頁 |
| 文件大小： | 357K |
| 代理商： | X5168S8I-4.5A-T1 |
6
FN8130.1
September 16, 2005
SPI Serial Memory
The memory portion of the device is a CMOS serial
EEPROM array with Intersil’s block lock protection. The
array is internally organized as x 8. The device features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
The device utilizes Intersil’s proprietary Direct Write cell,
providing a minimum endurance of 100,000 cycles and a
minimum data retention of 100 years.
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families. It contains an 8-bit
instruction register that is accessed via the SI input, with
data being clocked in on the rising edge of SCK. CS must be
LOW during the entire operation.
All instructions (Table 1), addresses and data are transferred
MSB first. Data input on the SI line is latched on the first
rising edge of SCK after CS goes LOW. Data is output on the
SO line by the falling edge of SCK. SCK is static, allowing
the user to stop the clock and then start it again to resume
operations where left off.
Write Enable Latch
The device contains a write enable latch. This latch must be
SET before a write operation is initiated. The WREN
instruction will set the latch and the WRDI instruction will
reset the latch (Figure 3). This latch is automatically reset
upon a power-up condition and after the completion of a
valid write cycle.
Status Register
The RDSR instruction provides access to the status register.
The status register may be read at any time, even during a
write cycle. The status register is formatted as follows:
The Write-In-Progress (WIP) bit is a volatile, read only bit
and indicates whether the device is busy with an internal
nonvolatile write operation. The WIP bit is read using the
RDSR instruction. When set to a “1”, a nonvolatile write
operation is in progress. When set to a “0”, no write is in
progress.
Note:
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
7
6
5
4
3210
WPEN
FLB
0
BL1
BL0
WEL
WIP
TABLE 1. INSTRUCTION SET
INSTRUCTION NAME
INSTRUCTION FORMAT*
OPERATION
WREN
0000 0110
Set the write enable latch (enable write operations)
SFLB
0000 0000
Set flag bit
WRDI/RFLB
0000 0100
Reset the write enable latch/reset flag bit
RSDR
0000 0101
Read status register
WRSR
0000 0001
Write status register (watchdog, block lock, WPEN & flag bits)
READ
0000 0011
Read data from memory array beginning at selected address
WRITE
0000 0010
Write data to memory array beginning at selected address
TABLE 2. BLOCK PROTECT MATRIX
WREN CMD
STATUS REGISTER
DEVICE PIN
BLOCK
STATUS REGISTER
WEL
WPEN
WP#
PROTECTED BLOCK
UNPROTECTED BLOCK
WPEN, BL0, BL1 WD0,
WD1
0
X
Protected
1
0
Protected
Writable
Protected
1
0
X
Protected
Writable
1
X
1
Protected
Writable
X5168, X5169
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