參數(shù)資料
型號(hào)： X5163PI-2.7
廠商： INTERSIL CORP
元件分類： 電源管理
英文描述： RTC Module With CPU Supervisor
中文描述： 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDIP8
封裝： PLASTIC, DIP-8
文件頁(yè)數(shù)： 8/21頁(yè)
文件大?。?/td> 117K
代理商： X5163PI-2.7
X5163/X5165 – Preliminary Information
Characteristics subject to change without notice.
8 of 21
REV 1.1 3/5/01
www.xicor.com
To write data to the EEPROM memory array, the user
then issues the WRITE instruction followed by the 16
bit address and then the data to be written. Any
unused address bits are specified to be “0’s”. The
WRITE operation minimally takes 32 clocks. CS must
go low and remain low for the duration of the operation.
If the address counter reaches the end of a page and
the clock continues, the counter will roll back to the first
address of the page and overwrite any data that may
have been previously written.
For the Page Write Operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of
the last data byte to be written is clocked in. If it is
brought HIGH at any other time, the write operation will
not be completed (Figure 4).
To write to the Status Register, the WRSR instruction is
followed by the data to be written (Figure 5). Data bits
0 and 1 must be “0”.
While the write is in progress following a Status Regis-
ter or EEPROM Sequence, the Status Register may be
read to check the WIP bit. During this time the WIP bit
will be high.
OPERATIONAL NOTES
The device powers-up in the following state:
– The device is in the low power standby state.
– A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
– SO pin is high impedance.
– The Write Enable Latch is reset.
– The Flag Bit is reset.
– Reset Signal is active for t
PURST
.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– A WREN instruction must be issued to set the Write
Enable Latch.
– CS must come HIGH at the proper clock count in
order to start a nonvolatile write cycle.
Figure 6. Read Status Register Sequence
0
1
2
3
4
5
6
7
8
9
10
11 12 13 14
7
6
5
4
3
2
1
0
Data Out
CS
SCK
SI
SO
MSB
High Impedance
Instruction
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