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參數(shù)資料
| 型號： | X5083S8IZ-2.7 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | RTC Module With CPU Supervisor |
| 中文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
| 封裝： | ROHS COMPLIANT, SOIC-8 |
| 文件頁數(shù)： | 3/21頁 |
| 文件大小： | 115K |
| 代理商： | X5083S8IZ-2.7 |
X5083
Characteristics subject to change without notice.
3 of 21
REV 1.1.6 6/25/02
www.xicor.com
PRINCIPLES OF OPERATION
Power On Reset
Application of power to the X5083 activates a power on
reset circuit. This circuit goes LOW at 1V and pulls the
RESET pin active. This signal prevents the system
microprocessor from starting to operate with insuffi-
cient voltage or prior to stabilization of the oscillator.
RESET active also blocks communication to the device
through the SPI interface. When V
device V
TRIP
value for 200ms (nominal) the circuit
releases RESET, allowing the processor to begin exe-
cuting code. While V
CC
< V
TRIP
device are inhibited.
CC
exceeds the
communications to the
Low Voltage Monitoring
During operation, the X5083 monitors the V
and asserts RESET if supply voltage falls below a pre-
set minimum V
TRIP
. The RESET signal prevents the
microprocessor from operating in a power fail or
brownout condition and terminates any SPI communi-
cation in progress. The RESET signal remains active
until the voltage drops below 1V. It also remains active
until V
CC
returns and exceeds V
CC
level
TRIP
for 200ms.
When V
progress are terminated and communications are
inhibited until V
CC
exceeds V
CC
falls below V
TRIP
, any communications in
TRIP
for t
PURST
.
Watchdog Timer
The watchdog timer circuit monitors the microprocessor
activity by monitoring the WDI input. The microprocessor
must toggle the CS/WDI pin periodically to prevent a
RESET signal. The CS/WDI pin must be toggled from
HIGH to LOW prior to the expiration of the watchdog time
out period. The state of two nonvolatile control bits in the
status register determine the watchdog timer period. The
microprocessor can change these watchdog bits with no
action taken by the microprocessor these bits remain
unchanged, even after total power failure.
V
The X5083 is shipped with a standard V
(V
TRIP
) voltage. This value will not change over normal
operating and storage conditions. However, in applica-
tions where the standard V
TRIP
higher precision is needed in the V
X5083 threshold may be adjusted. The procedure is
described below, and uses the application of a high
voltage control signal.
CC
Threshold Reset Procedure
CC
threshold
is not exactly right, or if
TRIP
value, the
Setting the V
This procedure is used to set the V
voltage value. For example, if the current V
and the new V
TRIP
is 4.6V, this procedure will directly
make the change. If the new setting is to be lower than
the current setting, then it is necessary to reset the trip
point before setting the new value.
TRIP
Voltage
TRIP
to a higher
TRIP
is 4.4V
To set the new V
threshold voltage to the V
the programming voltage V
mand, followed by a write of Data 00h to address 01h.
CS going HIGH on the write operation initiates the
V
TRIP
programming sequence. Bring WP LOW to com-
plete the operation.
TRIP
voltage, apply the desired V
CC
pin and tie the WP pin to
P
. Then send a WREN com-
TRIP
Note:
01h.
This operation also writes 00h to array address
Figure 1. Set V
TRIP
Level Sequence (V
CC
= desired V
TRIP
value)
0
1
2 3
4
5 6
7
SCK
SI
CS
06h
WREN
0
1
2 3
4
5 6
7 8
9 10
20 21 22 23
16 Bits
0001h
Address
02h
Write
WP
V
P
= 15-18V
00h
Data
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