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參數(shù)資料
| 型號： | X5045M8I-2.7 |
| 元件分類： | CPU監(jiān)測 |
| 英文描述： | RTC Module With CPU Supervisor |
| 中文描述： | 時鐘模塊CPU監(jiān)控 |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 108K |
| 代理商： | X5045M8I-2.7 |
X5043/X5045
Characteristics subject to change without notice.
9 of 20
REV 1.1.2 5/29/01
www.xicor.com
Figure 9. Write Memory Sequence
24 25 26 27 28 29 30 31
SCK
SI
CS
0
1
2
3
4
5
6
7
8
9
10
SCK
SI
Instruction
8 Bit Address
5
Data Byte 1
4
3
7
6
5
2
1
0
CS
32 33 34 35 36 37 38 39
Data Byte 2
5
4
7
6
3
2
1
0
Data Byte 3
5
4
7
6
3
2
1
0
Data Byte N
4
3
7
6
3
2
1
0
12 13 14 15 16 17 18 19 20 21 22 23
6
5
2
1
0
9
th
Bit of Address
8
OPERATIONAL NOTES
The device powers-up in the following state:
– The device is in the low power standby state.
– A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
– SO pin is high impedance.
– The Write Enable Latch is reset.
– The Flag Bit is reset.
– Reset Signal is active for t
PURST
.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– A WREN instruction must be issued to set the Write
Enable Latch.
– CS must come HIGH at the proper clock count in
order to start a nonvolatile write cycle.
– Block Protect bits provide additional level of write
protection for the memory array.
– The WP pin LOW blocks nonvolatile write operations.
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