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參數(shù)資料
| 型號： | X5001S8-4.5A |
| 英文描述： | Multi-Purpose Cleaner; Dispensing Method:Spray; Trade Name, Chemical:Dose n' Fill; Volume:32fl.oz. (US) RoHS Compliant: NA |
| 中文描述： | CPU監(jiān)控 |
| 文件頁數(shù)： | 2/19頁 |
| 文件大小： | 100K |
| 代理商： | X5001S8-4.5A |
X5001
2
PIN DESCRIPTION
Figure 1. PIN CONFIGURATION
PIN
(SOIC/PDIP)
PIN
TSSOP
Name
Function
1
1
CS/WDI
Chip Select Input.
a high impedance state. Unless a nonvolatile write cycle is underway, the de-
vice will be in the standby power mode. CS LOW enables the device, placing it
in the active power mode. Prior to the start of any operation after power up, a
HIGH to LOW transition on CS is required
Watchdog Input.
A HIGH to LOW transition on the WDI pin restarts the Watch-
dog timer. The absence of a HIGH to LOW transition within the watchdog time-
out period results in RESET/RESET going active.
Serial Output.
SO is a push/pull serial data output pin. A read cycle shifts data
out on this pin. The falling edge of the serial clock (SCK) clocks the data out.
Serial Input.
SI is a serial data input pin. Input all opcodes, byte addresses, and
memory data on this pin. The rising edge of the serial clock (SCK) latches the
input data. Send all opcodes (Table 1), addresses and data MSB first.
Serial Clock.
The Serial Clock controls the serial bus timing for data input and
output. The rising edge of SCK latches in the opcode, address, or watchdog
bits present on the SI pin. The falling edge of SCK changes the data output on
the SO pin.
V
TRIP
Program Enable.
When V
PE
is LOW, the V
valid programmed level. To readjust the V
be pulled to a high voltage (15-18V).
CS HIGH, deselects the device and the SO output pin is at
2
2
SO
5
8
SI
6
9
SCK
3
6
V
PE
TRIP
point is fixed at the last
level, requires that the VPE pin
TRIP
4
7
V
SS
Ground
8
14
V
CC
Supply Voltage
Reset Output
whenever Vcc falls below the minimum Vcc sense level. It will remain active un-
til Vcc rises above the minimum Vcc sense level for 200ms. RESET goes active
if the Watchdog Timer is enabled and CS/WDI remains either HIGH or LOW
longer than the selectable Watchdog time-out period. A falling edge of CS/WDI
will reset the Watchdog Timer. RESET goes active on power up at 1V and re-
mains active for 200ms after the power supply stabilizes.
No internal connections
7
13
RESET
.
RESET is an active LOW, open drain output which goes active
3-5,10-12
NC
8 Lead SOIC/PDIP
X
CS/WDI
SO
V
PE
1
2
3
4
RESET
SCK
SI
8
7
6
5
VCC
VSS
SCK
SI
VSS
V
PE
V
CC
CS/WDI
SO
1
2
3
4
8
7
6
5
8 Lead TSSOP
X
RESET
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