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參數(shù)資料
| 型號： | X4645S8-4.5A |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | CPU Supervidor with 64K EEPROM |
| 中文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
| 封裝： | PLASTIC, SOIC-8 |
| 文件頁數(shù)： | 6/22頁 |
| 文件大?。?/td> | 408K |
| 代理商： | X4645S8-4.5A |
X4643/5 – Preliminary Information
Characteristics subject to change without notice.
6 of 22
REV 1.26 4/30/02
www.xicor.com
The X4643/5 resets itself after the first byte is read.
The master should supply a stop condition to be con-
sistent with the bus protocol, but a stop is not required
to end this operation.
BP2, BP1, BP0: Block Protect Bits (Nonvolatile)
The Block Protect Bits, BP2, BP1 and BP0, determine
which blocks of the array are write protected. A write to
a protected block of memory is ignored. The block pro-
tect bits will prevent write operations to the following
segments of the array.
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the
Control Register.
WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the memory and to
the Register during a write operation. This bit is a vola-
tile latch that powers up in the LOW (disabled) state.
While the WEL bit is LOW, writes to any address,
including any control registers will be ignored (no
acknowledge will be issued after the Data Byte). The
WEL bit is set by writing a “1” to the WEL bit and
zeroes to the other bits of the control register. Once
set, WEL remains set until either it is reset to 0 (by writ-
ing a “0” to the WEL bit and zeroes to the other bits of
the control register) or until the part powers up again.
Writes to the WEL bit do not cause a nonvolatile write
cycle, so the device is ready for the next operation
immediately after the stop condition.
WD1, WD0: Watchdog Timer Bits
The bits WD1 and WD0 control the period of the
Watchdog Timer. The options are shown below.
Write Protect Enable
These devices have an advanced block lock scheme that
protects one of five blocks of the array when enabled. It
provides hardware write protection through the use of a
WP pin and a nonvolatile Write Protect Enable (WPEN)
bit.
The Write Protect (WP) pin and the Write Protect
Enable (WPEN) bit in the Control Register control the
programmable Hardware Write Protect feature. Hard-
ware Write Protection is enabled when the WP pin and
the WPEN bit are HIGH and disabled when either the
WP pin or the WPEN bit is LOW. When the chip is Hard-
ware Write Protected, nonvolatile writes to the block pro-
tected sections in the memory array cannot be written
and the block protect bits cannot be changed. Only the
sections of the memory array that are not block pro-
tected can be written. Note that since the WPEN bit is
write protected, it cannot be changed back to a LOW
state; so write protection is enabled as long as the WP
pin is held HIGH.
7
6
5
4
3
2
1
0
WPEN
WD1
WD0
BP1
BP0
RWEL WEL BP2
B
B
B
Protected Addresses
(Size)
None (factory setting)
None
None
0000h - 1FFFh
(8K bytes)
000h - 03Fh
(64 bytes)
000h - 07Fh
(128 bytes)
000h - 0FFh
(256 bytes)
000h - 1FFh
(512 bytes)
Array Lock
None
None
None
Full Array (All)
First Page (P1)
First 2 pgs (P2)
First 4 pgs (P4)
First 8 pgs (P8)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
WD1
0
0
1
1
WD0
0
1
0
1
Watchdog Time Out Period
1.4 seconds
600 milliseconds
200 milliseconds
disabled (factory setting)
Table 1. Write Protect Enable Bit and WP Pin Function
WP
LOW
HIGH
HIGH
WPEN
X
0
1
Memory Array not
Block Protected
Writes OK
Writes OK
Writes OK
Memory Array
Block Protected
Writes Blocked
Writes Blocked
Writes Blocked
Block Protect
Bits
Writes OK
Writes OK
Writes Blocked
WPEN Bit
Writes OK
Writes OK
Writes Blocked
Protection
Software
Software
Hardware
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| X4645S8I-2.7A | 功能描述:IC SUPERVISOR CPU 64K EE 8-SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標準包裝:100 系列:- 類型:簡單復位/加電復位 監(jiān)視電壓數(shù)目:1 輸出:- 復位:低有效 復位超時:最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:8-TSSOP 包裝:管件 |
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