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參數(shù)資料
| 型號(hào)： | X4165V8I |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | CPU Supervisor with 16K EEPROM |
| 中文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8 |
| 封裝： | PLASTIC, MO-153AC, TSSOP-8 |
| 文件頁數(shù)： | 12/23頁 |
| 文件大?。?/td> | 118K |
| 代理商： | X4165V8I |
X46402
Characteristics subject to change without notice.
12 of 23
Figure 12. Acknowledge Polling
8th CLK
of 8th
Pwd. Byte
‘ACK’
CLK
8th
CLK
‘ACK’
CLK
‘ACK’
START
Condition
8th Bit
ACK or
no ACK
SCL
SDA
PASSWORD PROTECTED READ OPERATIONS
Password protected read operations are initiated in the
same manner as password protected write operations
but with a different command code.
Password Random Read (Data Array, OTP Arrays)
Data from a password protected array can be randomly
read after sending a single password. To do this, the
master issues a start bit, sends a Password Read
instruction and read password, performs Password Ack
Polling, then issues the desired 2 byte address. The
host receives the first byte from the X46402 and sends
a NACK, followed by a repeated start bit. A new 8-bit
address specifies the next byte to read. This process
can continue indefinitely as long as the each byte read
out of the X46402 is “NACKed” and followed by a
repeated start.
The address automatically increments after each read
operation. As such, a special case arises. A random
read of address 00FFh automatically increments to
0100h after reading the byte. Consider the following
example.
Example: A system needs data from password pro-
tected locations 0020h and 0150h and the designer
does not wish to send the password twice. After receiv-
ing data from 0020h, the host sends a NACK and a
repeated start, followed by address byte FFh. The data
read from location 0FFh is ignored, but the operation
has adjusted the address pointer to 100h. Another
NACK and repeated start followed by the address 50h
allows the contents of 150h to be read by the host.
A random read of either of the OTP arrays can access
all locations of both arrays without another password
command sequence.
A password random read operation will also return
valid data if accessing a non-password protected area
of the array. See Figure 13.
Password Sequential Read
The host can read sequentially within an array after the
password acceptance sequence. The data output is
sequential, with the data from address n followed by
the data from n+1. The address counter for read opera-
tions increments all address bits, allowing the entire
memory array contents to be serially read during one
operation. At the end of the address space (address
1FFFh for the memory array, 7Fh for the OTP array)
the device goes into an idle state and data output is all
“1s”. To continue reading at another address requires a
new Read operation. Refer to Figure 14 for the
address, acknowledge and data transfer sequence. An
acknowledge must follow each 8-bit data transfer. After
the last bit has been read, the host sends a stop condi-
tion with or without a preceding acknowledge.
After sending a Password Read command and the cor-
rect password, the entire array, including non-pass-
word protected areas will be read with a sequential
read command.
After sending a Password Array Read command and cor-
rect password, the entire array, including non-password
protected areas are read by a sequential read command.
NON-PASSWORD READ OPERATIONS
Non-password protected read operations are initiated
in the same manner as non-password protected write
operations but with a different command code.
No-Password Random Read
The master issues the start condition, then a No-
password Read instruction, then issues the word
address. Once the first byte has been read, another
start can be issued followed by a new 8-bit address. A
No-Password random read operation is not allowed to a
password protected area. In a No-Password Random
Read from address 00FFh, the address pointer changes
to 100h after outputting the data byte and operates in
the same manner as the password protected operation.
See Figure 15.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| X4165V8I-2.7 | 功能描述:IC SUPERVISOR CPU 16K EE 8-TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 類型:簡(jiǎn)單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:- 復(fù)位:低有效 復(fù)位超時(shí):最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件 |
| X4165V8I-2.7A | 功能描述:IC SUPERVISOR CPU 16K EE 8-TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 類型:簡(jiǎn)單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:- 復(fù)位:低有效 復(fù)位超時(shí):最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件 |
| X4165V8I-4.5A | 功能描述:IC SUPERVISOR CPU 16K EE 8-TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 類型:簡(jiǎn)單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:- 復(fù)位:低有效 復(fù)位超時(shí):最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件 |
| X41D255 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| X41K1 | 制造商:ABB Low Voltage Products and Systems 功能描述:CCT,1KVA,460V,SINGLE |
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