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參數(shù)資料
| 型號： | X4043P8-2.7 |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁數(shù)： | 13/25頁 |
| 文件大?。?/td> | 144K |
| 代理商： | X4043P8-2.7 |
X4043/45
Characteristics subject to change without notice.
13 of 25
REV 1.1.17 9/14/01
www.xicor.com
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– The WEL bit must be set to allow write operations.
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile write
cycle.
– A three step sequence is required before writing into
the control register to change watchdog timer or
block lock settings.
– The WP pin, when held HIGH, prevents all writes to
the array and the control register.
– Communication to the device is inhibited as a result
of a low voltage condition (V
CC
< V
TRIP
)any in-
progress communication is terminated.
– Block lock bits can protect sections of the memory
array from write operations.
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Changing:
State Not
Known
Center Line
is High
Impedance
相關PDF資料 |
PDF描述 |
|---|---|
| X4043P8-2.7A | F22V10C FAMILY,500 GATE SPLD,5V,24-PIN(EPLD) |
| X4043P8-4.5A | 10NS, TSSOP, IND TEMP(EPLD) |
| X4043P8I | 15NS, PLCC, IND TEMP(EPLD) |
| X4043P8I-2.7 | Analog IC |
| X4043P8I-2.7A | 15NS, SOIC, IND TEMP(EPLD) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| X4043P8-4.5A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| X4043P8I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| X4043P8I-2.7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| X4043P8I-2.7A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| X4043P8I-4.5A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
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