參數(shù)資料
型號: X40430S14IZ-A
廠商: INTERSIL CORP
元件分類: 電源管理
英文描述: Triple Voltage Monitor with Integrated CPU Supervisor
中文描述: 3-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14
封裝: 0.150 INCH, ROHS COMPLIANT, SOIC-14
文件頁數(shù): 10/26頁
文件大?。?/td> 399K
代理商: X40430S14IZ-A
10
FN8251.1
May 24, 2006
Figure 5. Sample V
TRIP
Reset Circuit
Figure 6. V
TRIPX
Set/Reset Sequence (X = 1, 2, 3)
WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the memory and to
the Register during a write operation. This bit is a vola-
tile latch that powers up in the LOW (disabled) state.
While the WEL bit is LOW, writes to any address,
including any control registers will be ignored (no
acknowledge will be issued after the Data Byte). The
WEL bit is set by writing a “1” to the WEL bit and
zeroes to the other bits of the control register.
1
6
2
7
14
13
9
8
X4043X
V
TRIP1
Adj.
V
P
SDA
SCL
μC
Adjust
Run
V2FAIL
V
TRIP2
Adj.
RESET
V
TRIPX
Programming
Apply V
CC
and Voltage
> Desired V
TRIPX
to V
X
Decrease V
X
Actual V
TRIPX -
Desired V
TRIPX
DONE
Set Higher V
X
Sequence
Error < MDE
| Error | < | MDE |
YES
NO
Error > MDE
+
Desired
V
TRIPX
<
Present Value
Execute
No
YES
Execute
V
TRIPX
Reset Sequence
Set V
X
= desired V
TRIPX
New V
X
applied =
Old V
X
applied + | Error |
New V
X
applied =
Old V
X
applied - | Error |
Execute Reset V
TRIPX
Sequence
Output Switches
Note:
X = 1, 2, 3
Let:
MDE = Maximum Desired Error
Vx = V
CC
, VxMON
MDE
+
Desired Value
MDE
Acceptable
Error Range
Error = Actual - Desired
X40430, X40431, X40434, X40435
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X40430S14IZ-B Triple Voltage Monitor with Integrated CPU Supervisor
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