- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376439 > X40030V14I-B (INTERSIL CORP) Dual Voltage Monitor with Intergrated CPU Supervisor PDF資料下載
參數(shù)資料
| 型號(hào)： | X40030V14I-B |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | Dual Voltage Monitor with Intergrated CPU Supervisor |
| 中文描述： | 3-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14 |
| 封裝： | 4.40 MM, PLASTIC, MO-153AC, TSSOP-14 |
| 文件頁數(shù)： | 7/21頁 |
| 文件大?。?/td> | 322K |
| 代理商： | X40030V14I-B |
7
FN8114.0
April 28, 2005
Figure 6. V
TRIPX
Set/Reset Sequence (X = 1, 2, 3)
WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the memory and to
the Register during a write operation. This bit is a vola-
tile latch that powers up in the LOW (disabled) state.
While the WEL bit is LOW, writes to any address,
including any control registers will be ignored (no
acknowledge will be issued after the Data Byte). The
WEL bit is set by writing a “1” to the WEL bit and
zeroes to the other bits of the control register.
Once set, WEL remains set until either it is reset to 0
(by writing a “0” to the WEL bit and zeroes to the other
bits of the control register) or until the part powers up
again. Writes to the WEL bit do not cause a high volt-
age write cycle, so the device is ready for the next
operation immediately after the stop condition.
PUP1, PUP0: Power Up Bits (Nonvolatile)
The Power Up bits, PUP1 and PUP0, determine the
t
PURST
time delay. The nominal power up times are
shown in the following table.
V
TRIPX
Programming
Apply V
CC
and Voltage
> Desired V
TRIPX
to V
X
Decrease V
X
Actual V
TRIPX -
Desired V
TRIPX
DONE
Set Higher V
X
Sequence
Error < MDE
–
| Error | < | MDE |
YES
NO
Error > MDE
+
Desired
V
TRIPX
<
Present Value
Execute
No
YES
Execute
V
TRIPX
Reset Sequence
Set V
X
= desired V
TRIPX
New V
X
applied =
Old V
X
applied + | Error |
New V
X
applied =
Old V
X
applied - | Error |
Execute Reset V
TRIPX
Sequence
Output Switches
Note:
X = 1, 2, 3
Let:
MDE = Maximum Desired Error
Vx = V
CC
, VxMON
MDE
+
Desired Value
MDE
–
Acceptable
Error Range
Error = Actual - Desired
PUP1
0
0
1
1
PUP0
0
1
0
1
Power on Reset Delay (
t
PURST
)
50ms
200ms (factory setting)
400ms
800ms
X40030, X40031, X40034, X40035
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X40030V14I-C | Dual Voltage Monitor with Intergrated CPU Supervisor |
| X40031V14-B | Dual Voltage Monitor with Intergrated CPU Supervisor |
| X40031V14-C | Dual Voltage Monitor with Intergrated CPU Supervisor |
| X40031V14I-A | Dual Voltage Monitor with Intergrated CPU Supervisor |
| X40031V14I-B | Development Kit; Kit Contents:PIC18F6722 Prototyping Board with Exercise Book, DC Adapter & Cables ; For Use With:CCS Compilers & PIC18F6722; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No RoHS Compliant: No |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X40030V14I-BT1 | 功能描述:IC VOLTAGE MONITOR TRPL 14-TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 類型:簡(jiǎn)單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:- 復(fù)位:低有效 復(fù)位超時(shí):最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件 |
| X40030V14I-C | 功能描述:IC VOLTAGE MONITOR TRPL 14-TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 類型:簡(jiǎn)單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:- 復(fù)位:低有效 復(fù)位超時(shí):最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件 |
| X40030V14I-CT1 | 功能描述:IC VOLTAGE MONITOR TRPL 14-TSSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 監(jiān)控器 系列:- 標(biāo)準(zhǔn)包裝:100 系列:- 類型:簡(jiǎn)單復(fù)位/加電復(fù)位 監(jiān)視電壓數(shù)目:1 輸出:- 復(fù)位:低有效 復(fù)位超時(shí):最小為 100 ms 電壓 - 閥值:4.38V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:8-TSSOP 包裝:管件 |
| X40030V14Z-B | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple Voltage Monitor with Integrated CPU Supervisor |
| X40030VA | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Triple Voltage Monitor with Integrated CPU Supervisor |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。