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參數(shù)資料
| 型號： | X28C64FMB-20 |
| 英文描述： | 5 Volt, Byte Alterable E2PROM |
| 中文描述： | 5伏，可變E2PROM的字節(jié) |
| 文件頁數(shù)： | 6/25頁 |
| 文件大?。?/td> | 110K |
| 代理商： | X28C64FMB-20 |
6
X28C64
HARDWARE DATA PROTECTION
The X28C64 provides three hardware features (com-
patible with X2864A) that protect nonvolatile data from
inadvertent writes.
Noise Protection—A
WE
pulse typically less than
20ns will not initiate a write cycle.
Default V
CC
Sense—All write functions are inhibited
when V
CC
is
≤
3V typically.
Write Inhibit—Holding either
OE
LOW,
WE
HIGH, or
CE
HIGH will prevent an inadvertent write cycle during
power-up and power-down, maintaining data integrity.
SOFTWARE DATA PROTECTION
The X28C64 offers a software controlled data protection
feature. The X28C64 is shipped from Xicor with the
software data protection NOT ENABLED; that is, the
device will be in the standard operating mode. In this
mode data should be protected during power-up/-down
operations through the use of external circuits. The host
would then have open read and write access of the
device once V
CC
was stable.
The X28C64 can be automatically protected during
power-up and power-down without the need for external
circuits by employing the software data protection fea-
ture. The internal software data protection circuit is
enabled after the first write operation utilizing the soft-
ware algorithm. This circuit is nonvolatile and will remain
set for the life of the device unless the reset command
is issued.
Once the software protection is enabled, the X28C64 is
also protected from inadvertent and accidental writes in
the powered-on state. That is, the software algorithm
must be issued prior to writing additional data to the
device.
SOFTWARE ALGORITHM
Selecting the software data protection mode requires
the host system to precede data write operations by a
series of three write operations to three specific ad-
dresses. Refer to Figure 6 and 7 for the sequence. The
three-byte sequence opens the page write window
enabling the host to write from one to sixty-four bytes of
data*. Once the page load cycle has been completed,
the device will automatically be returned to the data
protected state.
Note: *Once the three-byte sequence s ssued t must be
followed by a valid byte or page write operation.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X28C64FMB-25 | 5 Volt, Byte Alterable E2PROM |
| X28C64J | 4-20MADC, EDGEWISE, MOD, APM - YOKOGAWA |
| X28C64JI | 5 Volt, Byte Alterable E2PROM |
| X28C64JM | 5 Volt, Byte Alterable E2PROM |
| X28C64T | 5 Volt, Byte Alterable E2PROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X28C64FMB-25 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:5 Volt, Byte Alterable E2PROM |
| X28C64GI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EEPROM |
| X28C64GI-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EEPROM |
| X28C64GI-25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EEPROM |
| X28C64GI-35 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EEPROM |
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