參數(shù)資料
型號: X25C02SI
英文描述: SPI Serial E2PROM
中文描述: 的SPI串行E2PROM
文件頁數(shù): 3/14頁
文件大小: 60K
代理商: X25C02SI
X25C02
3
PRINCIPLES OF OPERATION
The X25C02 is a 256 x 8 E
2
PROM designed to interface
directly with the synchronous serial peripheral interface
(SPI) of many popular microcontroller families.
The X25C02 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in on
the rising SCK.
CS
must be LOW and the
HOLD
and
WP
inputs must be HIGH during the entire operation.
Table 1 contains a list of the instructions and their
opcodes. All instructions, addresses and data are trans-
ferred MSB first.
Data input is sampled on the first rising edge of SCK after
CS
goes LOW. SCK is static, allowing the user to stop
the clock and then resume operations. If the clock line is
shared with other peripheral devices on the SPI bus, the
user can assert the
HOLD
input to place the X25C02 into
a “PAUSE” condition. After releasing
HOLD
, the X25C02
will resume operation from the point when
HOLD
was
first asserted.
Write Enable (WREN) and Write Disable (WRDI)
The X25C02 contains a “write enable” latch. This latch
must be SET before a write operation will be completed
internally. The WREN instruction will set the latch and
the WRDI instruction will reset the latch. This latch is
automatically reset upon a power-up condition and after
the completion of a byte or page write cycle. The latch is
also reset if
WP
is brought LOW.
Table 1. Instruction Set
Instruction Name
WREN
WRDI
Instruction Format*
0000 0110
0000 0100
Operation
Set the Write Enable Latch (Enable Write Operations)
Reset the Write Enable Latch (Disable Write Operations)
Read Data from Memory Array beginning at selected ad-
dress
Write Data to Memory Array beginning at Selected Address
(1 to 4 Bytes)
READ
0000 0011
WRITE
0000 0010
3843 PGM T02
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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