參數(shù)資料
型號: X25330S8-2.5
英文描述: 16 Characters x 2 Lines, 5x7 Dot Matrix Character and Cursor
中文描述: 5MHz的SPI串行e的2座門鎖TM保護(hù)胎膜早破
文件頁數(shù): 5/14頁
文件大小: 74K
代理商: X25330S8-2.5
X25330
5
Hold Operation
The HOLD input should be HIGH (at V
operation. If a data transfer is to be interrupted HOLD
can be pulled LOW to suspend the transfer until it can
be resumed. The only restriction is the SCK input must
be LOW when HOLD is first pulled LOW and SCK
must also be LOW when HOLD is released.
IH
) under normal
The HOLD input may be tied HIGH either directly to
V
CC
or tied to V
CC
through a resistor.
Operational Notes
The X25330 powers-up in the following state:
The device is in the low power standby state.
A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
SO pin is high impedance.
The “write enable” latch is reset.
Data Protection
The following circuitry has been included to prevent in-
advertent writes:
The “write enable” latch is reset upon power-up.
A WREN instruction must be issued to set the “write
enable” latch.
CS must come HIGH at the proper clock count in or-
der to start a write cycle.
Figure 1. Read E
2
PROM Array Operation Sequence
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24
25 26 27 28 29
30
7
6
5
4
3
2
1
0
DATA OUT
CS
SCK
SI
SO
MSB
HIGH IMPEDANCE
INSTRUCTION
16 BIT ADDRESS
15 14 13
3
2
1
0
7037 FRM F03
Figure 2. Read Status Register Operation Sequence
0
1
2
3
4
5
6
7
8
9
10 11
12 13 14
7
6
5
4
3
2
1
0
DATA OUT
CS
SCK
SI
SO
MSB
HIGH IMPEDANCE
INSTRUCTION
7037 FRM F04
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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