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參數(shù)資料
| 型號(hào)： | X25323S8I-2.7 |
| 英文描述： | Programmable Watchdog Timer & V CC Supervisory Circuit w/Serial E 2 PROM |
| 中文描述： | 可編程看門狗定時(shí)器 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大小： | 76K |
| 代理商： | X25323S8I-2.7 |
X25643/45
X25323/25
X25163/65
3
PRINCIPLES OF OPERATION
The device is designed to interface directly with the syn-
chronous Serial Peripheral Interface (SPI) of many popu-
lar microcontroller families.
The device monitors the bus and asserts RESET/RESET
output if there is no bus activity within user programmable
time-out period or the supply voltage falls below a preset
minimum V
trip
. The device contains an 8-bit instruction
register. It is accessed via the SI input, with data being
clocked in on the rising edge of SCK. CS must be LOW
during the entire operation.
All instructions
ferred MSB first. Data input on the SI line is latched on the
first rising edge of SCK after CS goes LOW. Data is out-
put on the SO line by the falling edge of SCK. SCK is
static, allowing the user to stop the clock and then start it
again to resume operations where left off.
(
Table 1), addresses and data are trans-
Write Enable Latch
The device contains a Write Enable Latch. This latch must
be SET before a Write Operation is initiated. The WREN
instruction will set the latch and the WRDI instruction will
reset the latch (Figure 3). This latch is automatically reset
upon a power-up condition and after the completion of a
valid Write Cycle.
Status Register
The RDSR instruction provides access to the Status Reg-
ister. The Status Register may be read at any time, even
during a Write Cycle. The Status Register is formatted as
follows:
The Write-In-Progress (WIP) bit is a volatile, read only bit
and indicates whether the device is busy with an internal
nonvolatile write operation. The WIP bit is read using the
RDSR instruction. When set to a “1”, a nonvolatile write
operation is in progress. When set to a “0”, no write is in
progress.
The Write Enable Latch (WEL) bit indicates the Status of
the Write Enable Latch. When WEL=1, the latch is set
HIGH and when WEL=0 the latch is reset LOW. The WEL
bit is a volatile, read only bit. It can be set by the WREN
instruction and can be reset by the WRDS instruction.
The Block Lock bits, BL0 and BL1, set the level of Block
Lock
Protection. These nonvolatile bits are pro-
grammed using the WRSR instruction and allow the user
to protect one quarter, one half, all or none of the
E
PROM array. Any portion of the array that is Block Lock
Protected can be read but not written. It will remain pro-
tected until the BL bits are altered to disable Block Lock
Protection of that portion of memory..
TM
2
7036 FRM T03
7
6
5
4
3
2
1
0
WPEN
FLB
WD1
WD0
BL1
BL0
WEL
WIP
7036 FRM T02
Status
Register
Bits
BL1 BL0
0
0
1
1
Array Addresses Protected
X2564x
X2532x
None
None
$1800–$1FFF $0C00–$0FFF $0600–$07FF
$1000–$1FFF $0800–$0FFF $0400–$07FF
$0000–$1FFF $0000–$0FFF $0000–$07FF
X2516x
None
0
1
0
1
Table 1. Instruction Set
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
7036 FRM T04
Instruction Name
WREN
Instruction Format*
0000 0110
Operation
Set the Write Enable Latch (Enable Write Operations)
Set Flag Bit
Reset the Write Enable Latch/Reset Flag Bit
Read Status Register
Write Status Register(Watchdog,BlockLock,WPEN & Flag Bits)
Read Data from Memory Array Beginning at Selected Address
Write Data to Memory Array Beginning at Selected Address
SFLB
0000 0000
WRDI/RFLB
0000 0100
RSDR
0000 0101
WRSR
0000 0001
READ
0000 0011
WRITE
0000 0010
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| X25323V14 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Programmable Watchdog Timer & V CC Supervisory Circuit w/Serial E 2 PROM |
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| X25323V14I | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Programmable Watchdog Timer & V CC Supervisory Circuit w/Serial E 2 PROM |
| X25323V14I-1.8 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Programmable Watchdog Timer & V CC Supervisory Circuit w/Serial E 2 PROM |
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