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參數(shù)資料
| 型號(hào)： | X25043PI-3 |
| 英文描述： | 100V Single N-Channel HEXFET Power MOSFET in a D2-Pak package; Similar to IRF3710STRL with Lead Free Packaging on Tape and Reel Left |
| 中文描述： | SPI串行EEPROM，帶有監(jiān)控功能 |
| 文件頁(yè)數(shù)： | 4/13頁(yè) |
| 文件大小： | 128K |
| 代理商： | X25043PI-3 |
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X25040
Characteristics subject to change without notice.
4 of 13
REV 1.1 7/12/00
www.xicor.com
be ignored.
and the data to be written. This is minimally a twenty-
four clock operation. CS must go LOW and remain
LOW for the duration of the operation. The host may
continue to write up to 16 bytes of data to the X25040.
The only restriction is the 16 bytes must reside on the
Clock and Data Timing
Data input on the SI line is latched on the rising edge
of SCK. Data is output on the SO line by the falling
edge of SCK.
Read Sequence
When reading from the EEPROM memory array, CS is
first pulled LOW to select the device. The 8-bit READ
instruction is transmitted to the X25040, followed by
the 8-bit address. Bit 3 of the Read Data instruction
contains address A
8
. This bit is used to select the
upper or lower half of the address. When A
half of the array ($0000–$0FFF) is selected. After the
read opcode and address are sent, the data stored in
the memory at the selected address is shifted out on
the SO line. The data stored in memory at the next
address can be read sequentially by continuing to pro-
vide clock pulses. The address is automatically incre-
mented to the next higher address after each byte of
data is shifted out. When the highest address is
reached ($1FF) the address counter rolls over to
address $000 allowing the read cycle to be continued
indefinitely. The read operation is terminated by taking
CS HIGH. Refer to the read EEPROM array operation
sequence illustrated in Figure 1.
8
= 0, lower
To read the status register, the CS line is first pulled
LOW to select the device followed by the 8-bit RDSR
instruction. After the read status register opcode is
sent, the contents of the status register are shifted out
on the SO line. Figure 2 illustrates the read status reg-
ister sequence.
Write Sequence
Prior to any attempt to write data into the X25040, the
“write enable” latch must first be set by issuing the
WREN instruction (See Figure 3). CS is first taken
LOW, then the WREN instruction is clocked into the
X25040. After all eight bits of the instruction are trans-
mitted, CS must then be taken HIGH. If the user con-
tinues the write operation without taking CS HIGH after
issuing the WREN instruction, the write operation will
To write data to the EEPROM memory array, the user
issues the WRITE instruction, followed by the address
same page. If the address counter reaches the end of
the page and the clock continues, the counter will “roll
over” to the first address of the page and overwrite any
data that may have been written.
For the write operation (byte or page write) to be com-
pleted, CS can only be brought HIGH after bit 0 of data
byte N is clocked in. If it is brought HIGH at any other
time the write operation will not be completed. Refer to
Figures 4 and 5 for a detailed illustration of the write
sequences and time frames in which CS going HIGH
are valid.
To write to the status register, the WRSR instruction is
followed by the data to be written. Data bits 0, 1, 4, 5, 6
and 7 must be “0”. Figure 6 illustrates this sequence.
While the write is in progress following a status register
or EEPROM write sequence, the status register may
be read to check the WIP bit. During this time the WIP
bit will be HIGH.
Hold Operation
The HOLD input should be HIGH (at V
operation. If a data transfer is to be interrupted HOLD
can be pulled LOW to suspend the transfer until it can
be resumed. The only restriction is the SCK input must
be LOW when HOLD is first pulled LOW and SCK must
also be LOW when HOLD is released.
IH
) under normal
The HOLD input may be tied HIGH either directly to
V
CC
or tied to V
CC
through a resistor.
Operational Notes
The X25040 powers-up in the following state:
– The device is in the low power standby state.
– A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
– SO pin is high impedance.
– The “write enable” latch is reset.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– The “write enable” latch is reset upon power-up.
– A WREN instruction must be issued to set the “write
enable” latch.
– CS must come HIGH at the proper clock count in
order to start a write cycle.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X25043S-3 | 55V Single N-Channel HEXFET Power MOSFET in a TO-220 FullPak (Iso) package; A IRLI2505 with Standard Packaging |
| X25043SI-3 | 40V Single N-Channel HEXFET Power MOSFET in a TO-262 package; Similar to IRL1404L with Lead Free Packaging |
| X25041S-2.7 | SPI Serial E2PROM with Block LockTM Protection |
| X25041S-3 | SPI Serial E2PROM with Block LockTM Protection |
| X25041SM-2.7 | SPI Serial E2PROM with Block LockTM Protection |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X25043S | 制造商:XICOR 制造商全稱(chēng):Xicor Inc. 功能描述:Programmable Watchdog Supervisory E2PROM |
| X25043S-2.7 | 制造商:XICOR 制造商全稱(chēng):Xicor Inc. 功能描述:Programmable Watchdog Supervisory E2PROM |
| X25043S-3 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:SPI Serial EEPROM with Supervisory Features |
| X25043SI | 制造商:Intersil Corporation 功能描述:Serial EEPROM, 512 x 8, 8 Pin, Plastic, SOP |
| X25043SI-2.7 | 制造商:Intersil Corporation 功能描述: |
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