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參數(shù)資料
| 型號： | X24C01SM-3.5 |
| 英文描述： | Serial E2PROM |
| 中文描述： | 串行E2PROM |
| 文件頁數(shù)： | 7/14頁 |
| 文件大?。?/td> | 56K |
| 代理商： | X24C01SM-3.5 |
X24C01
7
Sequential Read
Sequential read is initiated in the same manner as the
byte read. The first data byte is transmitted as with the
byte read mode, however, the master now responds
with an acknowledge, indicating it requires additional
data. The X24C01 continues to output data for each
acknowledge received. The read operation is termi-
nated by the master; by not responding with an acknowl-
edge and by issuing a stop condition.
The data output is sequential, with the data from address
n followed by the data from n + 1. The address counter
for read operations increments all address bits, allowing
the entire memory contents to be serially read during
one operation. At the end of the address space (address
127) the counter “rolls over” to zero and the X24C01
continues to output data for each acknowledge re-
ceived. Refer to Figure 8 for the address, acknowledge
and data transfer sequence.
Figure 8. Sequential Read
3837 FHD F13
Figure 9. Typical System Configuration
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
PULL-UP
RESISTORS
SDA
SCL
VCC
3837 FHD F14
BUS ACTIVITY:
SDA LINE
BUS ACTIVITY:
X24C01
ADDRESS
A
C
K
A
C
K
DATA n+x
S
T
O
P
P
DATA n
A
C
K
DATA n+1
A
C
K
DATA n+2
R
/
W
相關PDF資料 |
PDF描述 |
|---|---|
| X24C01M | Serial E2PROM |
| X24C01MI | Serial E2PROM |
| X24C01MM | Serial E2PROM |
| X24C01P | Serial E2PROM |
| X24C01PI | Serial E2PROM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| X24C01SMG | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Serial E2PROM |
| X24C01SMG-2.7 | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Serial E2PROM |
| X24C01SMG-3 | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Serial E2PROM |
| X24C01SMG-3.5 | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Serial E2PROM |
| X24C02 | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Serial E2PROM |
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