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參數(shù)資料
| 型號： | X24C01AS8-3.5 |
| 英文描述： | Serial E2PROM |
| 中文描述： | 串行E2PROM |
| 文件頁數(shù)： | 4/13頁 |
| 文件大小： | 58K |
| 代理商： | X24C01AS8-3.5 |
X24C01A
4
DEVICE ADDRESSING
Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave address are the device type
identifier (see Figure 4). For the X24C01A this is fixed as
1010[B].
Following the start condition, the X24C01A monitors the
SDA bus comparing the slave address being transmit-
ted with its slave address (device type and state of A
0
,
A
1
and A
2
inputs). Upon a correct compare the X24C01A
outputs an acknowledge on the SDA line. Depending on
the state of the R/
W
bit, the X24C01A will execute a read
or write operation.
WRITE OPERATIONS
Byte Write
For a write operation, the X24C01A requires a second
address field. This address field is the word address,
comprised of eight bits, providing access to any one of
the 128 words of memory. Note: the most significant bit
is a don’t care. Upon receipt of the word address the
X24C01A responds with an acknowledge, and awaits
the next eight bits of data, again responding with an
acknowledge. The master then terminates the transfer
by generating a stop condition, at which time the X24C01A
begins the internal write cycle to the nonvolatile memory.
While the internal write cycle is in progress the X24C01A
inputs are disabled, and the device will not respond to
any requests from the master. Refer to Figure 5 for the
address, acknowledge and data transfer sequence.
Figure 4. Slave Address
The next three significant bits address a particular
device. A system could have up to eight X24C01A
devices on the bus (see Figure 10). The eight addresses
are defined by the state of the A
0
, A
1
and A
2
inputs.
The last bit of the slave address defines the operation to
be performed. When set to one a read operation is
selected, when set to zero a write operation is selected.
Figure 5. Byte Write
Figure 6. Page Write
1
0
1
0
A2
A1
A0
R/W
DEVICE TYPE
IDENTIFIER
DEVICE
ADDRESS
3841 FHD F08
3841 FHD F09
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
X24C01A
S
T
A
R
T
SLAVE
ADDRESS
S
S
T
O
P
P
A
C
K
A
C
K
A
C
K
WORD
ADDRESS
DATA
3841 FHD F10
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
X24C01A
S
T
A
R
T
SLAVE
ADDRESS
S
S
T
O
P
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
WORD ADDRESS n
DATA n
DATA n–1
DATA n+3
NOTE: In this example n = xxxx 0000 (B); x = 1 or 0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X24C01AP | Isolated Flyback Switching Regulator with 9V Output |
| X24C01API | Isolated Flyback Switching Regulator with 9V Output |
| X24C01API-3 | Isolated Flyback Switching Regulator with 9V Output |
| X24C01AS8I-3 | Serial E2PROM |
| X24C01AS8M-3 | Serial E2PROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X24C01AS8G | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Serial E2PROM |
| X24C01AS8G-3 | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Serial E2PROM |
| X24C01AS8G-3.5 | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Serial E2PROM |
| X24C01AS8I | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Serial E2PROM |
| X24C01AS8I-2.7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:I2C Serial EEPROM |
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