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參數(shù)資料
| 型號： | X24C01AP-3 |
| 英文描述： | Serial E2PROM |
| 中文描述： | 串行E2PROM |
| 文件頁數(shù)： | 7/13頁 |
| 文件大?。?/td> | 58K |
| 代理商： | X24C01AP-3 |
X24C01A
7
Sequential Read
Sequential Read can be initiated as either a current
address read or random access read. The first word is
transmitted as with the other modes, however, the
master now responds with an acknowledge, indicating it
requires additional data. The X24C01A continues to
output data for each acknowledge received. The read
operation is terminated by the master, by not responding
with an acknowledge and by issuing a stop condition.
The data output is sequential, with the data from address
n followed by the data from n + 1. The address counter
for read operations increments all address bits, allowing
the entire memory contents to be serially read during
one operation. At the end of the address space (address
127), the counter “rolls over” to address 0 and the
X24C01A continues to output data for each acknowl-
edge received. Refer to Figure 9 for the address, ac-
knowledge and data transfer sequence.
Figure 9. Sequential Read
Figure 10. Typical System Configuration
3841 FHD F14
3841 FHD F15
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
VCC
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
X24C01A
SLAVE
ADDRESS
A
C
K
A
C
K
DATA n+x
S
T
O
P
P
DATA n
A
C
K
DATA n+1
A
C
K
DATA n+2
相關PDF資料 |
PDF描述 |
|---|---|
| X24C01AP-3.5 | Serial E2PROM |
| X24C01P-2.7 | Serial E2PROM |
| X24C01P-3 | Serial E2PROM |
| X24C01P-3.5 | Serial E2PROM |
| X24C01S-2.7 | Serial E2PROM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| X24C01AP-3.5 | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Serial E2PROM |
| X24C01APG | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Serial E2PROM |
| X24C01APG-3 | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Serial E2PROM |
| X24C01APG-3.5 | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Serial E2PROM |
| X24C01API | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Serial E2PROM |
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