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參數(shù)資料
| 型號(hào)： | X24641S8-2.5 |
| 英文描述： | 400 KHz 2-Wire Serial E 2 PROM |
| 中文描述： | 400千赫2線串行首頁2 PROM的 |
| 文件頁數(shù)： | 7/13頁 |
| 文件大?。?/td> | 66K |
| 代理商： | X24641S8-2.5 |
X24641
7
Acknowledge Polling
The maximum write cycle time can be significantly
reduced using Acknowledge Polling. To initiate
Acknowledge Polling, the master issues a start condi-
tion followed by the Slave Address Byte for a write or
read operation. If the device is still busy with the
nonvolatile write cycle, then no ACK will be returned. If
the device has completed the nonvolatile write opera-
tion, an ACK will be returned and the host can then
proceed with the read or write operation. Refer to
figure 6.
BYTE LOAD COMPLETED
BY ISSUING STOP.
ENTER ACK POLLING
ISSUE
START
ISSUE SLAVE
ADDRESS BYTE
(READ OR PROGRAM)
ACK
RETURNED
NONVOLATILE
WRITE
CYCLE COMPLETE.
CONTINUE
SEQUENCE
CONTINUE NORMAL
READ ORPROGRAM
COMMAND SEQUENCE
PROCEED
ISSUE STOP
NO
YES
YES
ISSUE STOP
NO
7026 FM 09
READ OPERATIONS
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads,
Random Reads, and Sequential Reads.
Current Address Read
Internally, the device contains an address counter that
maintains the address of the last byte read or written,
incremented by one. After a read operation from the
last address in the array, the counter will “roll over” to
the first address in the array. After a write operation to
the last address in a given page, the counter will “roll
over” to the first address of the same page.
Upon receipt of the Slave Address Byte with the R/W
bit set to one, the device issues an acknowledge and
then transmits the byte at the current address. The
master terminates the read operation when it does not
respond with an acknowledge during the ninth clock
and then issues a stop condition. Refer to figure 7 for
the address, acknowledge, and data transfer
sequence.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
FROM THE
SLAVE
S
T
A
R
T
S
SLAVE
ADDRESS
S
T
O
P
P
A
C
K
DATA
SIGNALS
FROM THE
MASTER
SDA BUS
SIGNALS
1
0 1 0
1
7026 FM 10
Figure 6. Acknowledge Polling Sequence
Figure 7. Current Address Read Sequence
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X24641S8I | 400 KHz 2-Wire Serial E 2 PROM |
| X24641S8I-2.5 | 400 KHz 2-Wire Serial E 2 PROM |
| X24645A | I2C Serial EEPROM |
| X24645A-2.7 | 30V Single N-Channel HEXFET Power MOSFET in a SO-8 package; Similar to IRF7821 with Lead Free Packaging |
| X24645AI | 20V Single N-Channel HEXFET Power MOSFET in a I-Pak package; A IRFU3711Z with Standard Packaging |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X24641S8I | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:400 KHz 2-Wire Serial E 2 PROM |
| X24641S8I-1.8 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:400 KHz 2-Wire Serial E 2 PROM |
| X24641S8I-2.5 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:400 KHz 2-Wire Serial E 2 PROM |
| X24645 | 制造商:XICOR 制造商全稱:Xicor Inc. 功能描述:Advanced 2-Wire Serial E 2 PROM with Block Lock TM Protection |
| X246458I-2.7TI | 制造商:Intersil Corporation 功能描述: |
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