參數(shù)資料
型號(hào): X24321S8I-2.5
元件分類: 數(shù)字電位計(jì)
英文描述: Series 940-F/947, 3000 mm [118.0 in] scan distance, Plastic M30, Prewired 2 m, switching output NPN, adjustment potentiometer
中文描述: 400千赫2線串行E2PROM
文件頁(yè)數(shù): 5/13頁(yè)
文件大?。?/td> 66K
代理商: X24321S8I-2.5
X24321
5
Figure 4. Device Addressing
1
S1
S0
R/W
DEVICE
SELECT
0
1
0
S2
DEVICE TYPE
IDENTIFIER
SLAVE ADDRESS BYTE
D7
D2
D1
D6
D5
D4
D3
DATA BYTE
A2
A1
A0
A5
LOW ORDER ADDRESS
A4
A3
ADDRESS BYTE 0
0
A10
A9
A8
0
HIGH ORDER ADDRESS
A11
ADDRESS BYTE 1
0
A7
A6
D0
7040 FM 06
A0
DEVICE ADDRESSING
Following a start condition, the master must output the
address of the slave it is accessing. The first four bits
of the Slave Address Byte are the device type identifier
bits. These must equal “1010”. The next 3 bits are the
device select bits S
0
, S
1
, and S
devices to share a single bus. These bits are
compared to the S
0
, S
1
, and S
pins. The last bit of the Slave Address Byte defines the
operation to be performed. When the R/W bit is a one,
then a Read Operation is selected. When it is zero
then a Write Operation is selected. Refer to figure 4.
After loading the Slave Address Byte from the SDA
bus, the device compares the device type bits with the
value “1010” and the device select bits with the status
2
. This allows up to 8
2
device select input
of the device select input pins. If the compare is not
successful, no acknowledge is output during the ninth
clock cycle and the device returns to the standby mode.
The byte address is either supplied by the master or
obtained from an internal counter, depending on the
operation. When required, the master must supply the
two Address Bytes as shown in figure 4.
The internal organization of the E
pages by 32 bytes per page. The page address is
partially contained in the Address Byte 1 and partially in
bits 7 through 5 of the Address Byte 0. The specific byte
address is contained in bits 4 through 0 of the Address
Byte 0. Refer to figure 4.
2
PROM array is 128
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