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參數(shù)資料
| 型號(hào)： | X24320V14G-1.8 |
| 廠商： | IC MICROSYSTEMS SDN BHD |
| 元件分類： | DRAM |
| 英文描述： | 400KHz 2-Wire Serial E2PROM with Block Lock |
| 中文描述： | 4K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO14 |
| 封裝： | ROHS COMPLIANT, PLASTIC, TSSOP-14 |
| 文件頁(yè)數(shù)： | 5/17頁(yè) |
| 文件大?。?/td> | 316K |
| 代理商： | X24320V14G-1.8 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)當(dāng)前第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)
X24320
5
Figure 4. Device Addressing
1
S1
S0
R/W
DEVICE
SELECT
0
1
0
S2
DEVICE TYPE
IDENTIFIER
SLAVE ADDRESS BYTE
D7
D2
D1
D6
D5
D4
D3
DATA BYTE
A2
A1
A0
A5
LOW ORDER WORD ADDRESS
A4
A3
WORD ADDRESS BYTE 0
0
A10
A9
A8
0
HIGH ORDER WORD ADDRESS
A11
X24320 WORD ADDRESS BYTE 1
0
0
A7
A6
D0
7035 FM 06
DEVICE ADDRESSING
Following a start condition, the master must output the
address of the slave it is accessing. The first four bits
of the Slave Address Byte are the device type identifier bits.
These must equal “1010”.
The next 3 bits are the
device select bits S
0
, S
1
, and S
2
. This allows up to 8 devices
to share a single bus. These bits are
compared to the S
0
, S
1
, and S
2
device select input pins.
The last bit of the Slave Address Byte defines the
operation to be performed. When the R/W bit is a one, then
a read operation is selected. When it is zero then
a write operation is selected. Refer to figure 4. After
loading the Slave Address Byte from the SDA bus, the
device compares the device type bits with the value
“1010”
and the device select bits with the status of the
device select input pins. If the compare is not successful, no
acknowledge is output during the ninth clock cycle
and the device returns to the standby mode.
The word address is either supplied by the master or
obtained from an internal counter, depending on the
operation. The master must supply the two Word Address
Bytes as shown in figure 4.
The internal organization of the E
2
array is 128 pages by 32
bytes per page. The page address is partially
contained in the Word Address Byte 1 and partially in bits 7
through 5 of the Word Address Byte 0. The byte
address is contained in bits 4 through 0 of the Word
Address Byte 0. See figure 4.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X24320V14G-2.5 | 400KHz 2-Wire Serial E2PROM with Block Lock |
| X24320V14IG | 400KHz 2-Wire Serial E2PROM with Block Lock |
| X24320V14IG-1.8 | 400KHz 2-Wire Serial E2PROM with Block Lock |
| X24320V14IG-2.5 | 400KHz 2-Wire Serial E2PROM with Block Lock |
| X24645F | Advanced 2-Wire Serial E2PROM with Block LockTM Protection |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X24320V14G-2.5 | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:400KHz 2-Wire Serial E2PROM with Block Lock |
| X24320V14I | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:400KHz 2-Wire Serial E2PROM with Block Lock |
| X24320V14I-1.8 | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:400KHz 2-Wire Serial E2PROM with Block Lock |
| X24320V14I-2.5 | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:400KHz 2-Wire Serial E2PROM with Block Lock |
| X24320V14IG | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:400KHz 2-Wire Serial E2PROM with Block Lock |
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