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參數(shù)資料
| 型號(hào)： | X24165VMG-2.7 |
| 廠商： | IC MICROSYSTEMS SDN BHD |
| 元件分類： | DRAM |
| 英文描述： | Advanced 2-Wire Serial E2PROM with Block LockTM Protection |
| 中文描述： | 2K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO14 |
| 封裝： | ROHS COMPLIANT, PLASTIC, TSSOP-14 |
| 文件頁(yè)數(shù)： | 3/17頁(yè) |
| 文件大?。?/td> | 305K |
| 代理商： | X24165VMG-2.7 |
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X24165
3
DEVICE OPERATION
The X24165 supports a bidirectional bus oriented pro-
tocol. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device as
the receiver. The device controlling the transfer is a
master and the device being controlled is the slave. The
master will always initiate data transfers, and provide
the clock for both transmit and receive operations.
Therefore, the X24165 will be considered a slave in all
applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer to
Figures 1 and 2.
Start Condition
All command are preceded by the start condition, which
is a HIGH to LOW transition of SDA when SCL is
HIGH. The X24165 continuously monitors the SDA and SCL
lines for the start condition and will not respond to
any command until this condition has been met.
SCL
SDA
DATA STABLE
DATA
CHANGE
6551 ILL F04
SCL
SDA
START BIT
STOP BIT
6551 ILL F05
Figure 1. Data Validity
Figure 2. Definition of Start and Stop
N
otes:
(5) Typical values are for T
A
= 25
°
C and nominal supply voltage (5V)
(6) t
WR
is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum
the device requires to perform the internal write operation.
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