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參數(shù)資料
| 型號： | X24165VIG-2.7 |
| 廠商： | IC MICROSYSTEMS SDN BHD |
| 元件分類： | DRAM |
| 英文描述： | Advanced 2-Wire Serial E2PROM with Block LockTM Protection |
| 中文描述： | 2K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO14 |
| 封裝： | ROHS COMPLIANT, PLASTIC, TSSOP-14 |
| 文件頁數(shù)： | 7/17頁 |
| 文件大?。?/td> | 305K |
| 代理商： | X24165VIG-2.7 |
X24165
7
Figure 7. Current Address Read
Figure 8. Random Read
READ OPERATIONS
Read operations are initiated in the same manner as
Write operations with the exception that the R/W bit
of the slave address is set HIGH. There are three basic read
operations: current address read, random read
and sequential read.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condition
during the ninth cycle or hold SDA HIGH during the
ninth clock cycle and then issue a stop condition.
Current Address Read
Internally the X24165 contains an address counter that
maintains the address of the last word read, incremented
by one or the exact address of the last word written.
Therefore, if the last access read was to address n, the
next read operation would access data from address
n + 1. Upon receipt of the slave address with the R/W
set HIGH, the X24165 issues an acknowledge and
transmits the eight-bit word. The read operation is
terminated by the master; by not responding with an acknow
-ledge and by issuing a stop condition. Refer to
Figure 7 for the sequence of address, acknowledge and
data transfer.
Random Read
Random read operations allow the master to access any
memory location in a random manner. Prior to issuing
the slave address with the R / W bit set HIGH, the master
must first perform a “dummy” write operation.
The master issues the start condition, and the slave ad-
dress with the R/W bit set LOW, followed by the word
address it is to read. After the word address acknowledge, the
master immediately reissues the start condition
and the slave address with the R/W bit set HIGH. This will be
followed by an acknowledge from the
X24165 and then by the eight-bit word. The read operation is
terminated by the master; by not responding
with an acknowledge and by issuing a stop condition. Refer
to Figure 8 for the address, acknowledge and
data transfer sequence.
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
X24165
S
T
A
R
T
SLAVE
ADDRESS
S
S
T
O
P
P
A
C
K
DATA
6551 ILL F11
BUS ACTIVITY:
MASTER
SDA LINE
BUS ACTIVITY:
X24165
S
T
A
R
T
SLAVE
ADDRESS
S
A
C
K
6551 ILL F12.1
S
T
A
R
T
S
WORD
ADDRESS n
A
C
K
SLAVE
ADDRESS
DATA n
A
C
K
S
T
O
P
P
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X24165VMG | Advanced 2-Wire Serial E2PROM with Block LockTM Protection |
| X24165VMG-2.7 | Advanced 2-Wire Serial E2PROM with Block LockTM Protection |
| X24320PIG-2.5 | 400KHz 2-Wire Serial E2PROM with Block Lock |
| X24320AFG | 400KHz 2-Wire Serial E2PROM with Block Lock |
| X24320AFP | 400KHz 2-Wire Serial E2PROM with Block Lock |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X24165VM | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Advanced 2-Wire Serial E2PROM with Block LockTM Protection |
| X24165VM-2.7 | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Advanced 2-Wire Serial E2PROM with Block LockTM Protection |
| X24165VMG | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Advanced 2-Wire Serial E2PROM with Block LockTM Protection |
| X24165VMG-2.7 | 制造商:ICMIC 制造商全稱:IC MICROSYSTEMS 功能描述:Advanced 2-Wire Serial E2PROM with Block LockTM Protection |
| X241-883B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:X200 SERIES (CMOS) STANDARD SPECFITIONS |
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