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參數(shù)資料
| 型號(hào)： | X24129 |
| 英文描述： | 16K×8Bit 400KHz 2-Wire Serial E2PROM(400KHz二線串行EEPROM) |
| 中文描述： | 16K的× 8位400kHz的2線串行E2PROM（400kHz的二線串行EEPROM的） |
| 文件頁(yè)數(shù)： | 6/13頁(yè) |
| 文件大?。?/td> | 64K |
| 代理商： | X24129 |
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X24129
6
Figure 5. Page Write Sequence
WRITE OPERATIONS
Byte Write
For a Byte Write Operation, the device requires the
Slave Address Byte, the Word Address Byte 1, and the
Word Address Byte 0, which gives the master access to
any one of the bytes in the array. Upon receipt of the
Word Address Byte 0, the device responds with an
acknowledge, and waits for the first eight bits of data.
After receiving the 8 bits of the data byte, the device
again responds with an acknowledge. The master then
terminates the transfer by generating a stop condition,
at which time the device begins the internal write cycle
to the nonvolatile memory. While the internal write cycle
is in progress the device inputs are disabled and the
device will not respond to any requests from the master.
The SDA pin is at high impedance. See figure 4.
Page Write Operation
The device executes a thirty-two byte Page Write
Operation. For a Page Write Operation, the device
requires the Slave Address Byte, Address Byte 1, and
Address Byte 0. Address Byte 0 must contain the first
byte of the page to be written. Upon receipt of Address
Byte 0, the device responds with an acknowledge, and
waits for the first eight bits of data. After receiving the 8
bits of the first data byte, the device again responds
with an acknowledge. The device will respond with an
acknowledge after the receipt of each of 31 more
bytes. Each time the byte address is internally incre-
mented by one, while page address remains constant.
When the counter reaches the end of the page, the
master terminates the data loading by issuing a stop
condition, which causes the device to begin the
nonvolatile write cycle. All inputs are disabled until
completion of the nonvolatile write cycle. The SDA pin
is at high impedance. Refer to figure 5 for the address,
acknowledge, and data transfer sequence.
S
T
A
R
T
SLAVE
ADDRESS
R
T
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
DATA
(1)
SIGNALS
FROM THE
MASTER
SDA BUS
SIGNALS
FROM THE
SLAVE
DATA
(32)
T
O
P
ADDRESS
BYTE 1
ADDRESS
BYTE 0
1 0 S
S
P
MASTER
SLAVE
S
T
SLAVE
S
A
C
K
A
C
K
A
C
K
A
C
K
BYTE 1
DATA
0
BYTE 0
P
7041 FM 07
SIGNALS
FROMTHE
MASTER
SDA BUS
SIGNALS
FROMTHE
SLAVE
S
T
A
R
T
S
SLAVE
ADDRESS
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
WORDADDRESS
BYTE 1
DATA
1 0 1 0
0
WORD ADDRESS
BYTE 0
P
7041 FM 07
Figure 4. Byte Write Sequence
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| X24129S | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:I2C Serial EEPROM |
| X24129S-1.8 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:I2C Serial EEPROM |
| X24129S-2.5 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:I2C Serial EEPROM |
| X24129SI | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:I2C Serial EEPROM |
| X24129SI-1.8 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:I2C Serial EEPROM |
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