參數(shù)資料
型號: X20C16
英文描述: High Speed AUTOSTORE NOVRAM(高速帶自動存貯的CMOS非易失性靜態(tài)RAM,帶非易失使能輸入,AUTOSTORE 輸出引腳。)
中文描述: 高速自動存儲NOVRAM(高速帶自動存貯的的CMOS非易失性靜態(tài)RAM的,帶非易失使能輸入,自動存儲輸出引腳。)
文件頁數(shù): 3/24頁
文件大?。?/td> 186K
代理商: X20C16
X20C16
3
DEVICE OPERATION
The
CE
,
OE
,
WE,
and
NE
inputs control the X20C16
operation. The X20C16 byte-wide NOVRAM uses a
2-line control architecture to eliminate bus contention in
a system environment. The I/O bus will be in a high
impedance state when either
OE
or
CE
is HIGH, or
when
NE
is LOW.
RAM Operations
RAM read and write operations are performed as they
would be with any static RAM. A read operation requires
CE
and
OE
to be LOW with
WE
and
NE
HIGH. A write
operation requires
CE
and
WE
to be LOW with
NE
HIGH. There is no limit to the number of read or write
operations performed to the RAM portion of the X20C16.
Memory Transfer Operations
There are two memory transfer operations: a recall
operation whereby the data stored in the E
2
PROM array
is transferred to the RAM array; and a store operation
which causes the entire contents of the RAM array to be
stored in the E
2
PROM array.
Recall operations are performed automatically upon
power-up and under host system control when
NE
,
OE
and
CE
are LOW and
WE
is HIGH. The recall operation
takes a maximum of 5
μ
s.
SDP (Software Data Protection)
There are two methods of initiating a store operation.
The first is the software store command. This command
takes the place of the hardware store employed on the
X20C04. This command is issued by entering into the
special command mode:
NE
,
CE,
and
WE
strobe LOW
while at the same time a specific address and data
combination is sent to the device. This is a three step
operation: the first address/data combination is 555[H]/
AA[H]; the second combination is 2AA[H]/55[H]; and the
final command combination is 555[H]/33[H]. This se-
quence of pseudo write operations will immediately
initiate a store operation. Refer to the software com-
mand timing diagrams for details on set and hold times
for the various signals.
The second method of storing data is with the
AUTOSTORE command. When enabled, data is auto-
matically stored from the RAM into the E
2
PROM array
whenever V
CC
falls below the preset Autostore thresh-
old. This feature is enabled by performing the first two
steps for the software store with the command combina-
tion being 555[H]/CC[H].
The AUTOSTORE feature is disabled by issuing the
three step command sequence with the command com-
bination being 555[H]/CD[H]. The AUTOSTORE feature
will also be reset if V
CC
falls below the power-up reset
threshold (approximately 3.5V) and is then raised back
into the operation range.
Write Protection
The X20C16 supports two methods of protecting the
nonvolatile data.
—If after power-up the AUTOSTORE feature is not
enabled, no AUTOSTORE can occur.
—V
CC
Sense – All functions are inhibited when V
CC
is
3.0V typical.
SYMBOL TABLE
The following symbol table provides a key to under-
standing the conventions used in the device timing
diagrams. The diagrams should be used in conjunction
with the device timing specifications to determine actual
device operation and performance, as well as device
suitability for user’s application.
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Changing:
State Not
Known
Center Line
is High
Impedance
相關(guān)PDF資料
PDF描述
X20C17 High Speed AUTOSTORE NOVRAM(高速帶自動存貯的CMOS非易失性靜態(tài)RAM,標(biāo)準(zhǔn)的24腳 DIP 封裝)
X2212AP NVRAM (EEPROM Based)
X2212DI 200V Single N-Channel HEXFET Power MOSFET in a TO-262 package; A IRFSL38N20D with Standard Packaging
X2212DM 75V Single N-Channel HEXFET Power MOSFET in a D-Pak package; Similar to IRFR2407 with Lead Free Packaging
X2212DMB NVRAM (EEPROM Based)
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