FN8102.3 April 14, 2006 Table 7. Crystal Parameters Required for Intersil RTC’s Table 8. Crystal Manufacturers A final application for the ATR " />
參數(shù)資料
型號(hào)： X1288S16I-2.7T1
廠商： Intersil
文件頁(yè)數(shù)： 16/27頁(yè)
文件大?。?/td> 0K
描述： IC RTC/CAL/CPU SUP EE 16-SOIC
標(biāo)準(zhǔn)包裝： 1,000
類(lèi)型： 時(shí)鐘/日歷
特點(diǎn)： 警報(bào)器，閏年，監(jiān)控器，監(jiān)視計(jì)時(shí)器
時(shí)間格式： HH:MM:SS:hh（12/24 小時(shí)）
數(shù)據(jù)格式： YY-MM-DD-dd
接口： I²C，2 線串口
電源電壓： 2.7 V ~ 5.5 V
電壓 - 電源，電池： 1.8 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 16-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC
包裝： 帶卷 (TR)
23
FN8102.3
April 14, 2006
Table 7. Crystal Parameters Required for Intersil RTC’s
Table 8. Crystal Manufacturers
A final application for the ATR control is in-circuit cali-
bration for high accuracy applications, along with a
temperature sensor chip. Once the RTC circuit is pow-
ered up with battery backup, the PHZ output is set at
32.768kHz and frequency drift is measured. The ATR
control is then adjusted to a setting which minimizes
drift. Once adjusted at a particular temperature, it is
possible to adjust at other discrete temperatures for
minimal overall drift, and store the resulting settings in
the EEPROM. Extremely low overall temperature drift
is possible with this method. The Intersil evaluation
board contains the circuitry necessary to implement
this control.
For more detailed operation see Intersil’s application
note AN154 on Intersil’s website at www.intersil.com.
Layout Considerations
The crystal input at X1 has a very high impedance and
will pick up high frequency signals from other circuits
on the board. Since the X2 pin is tied to the other side
of the crystal, it is also a sensitive node. These signals
can couple into the oscillator circuit and produce dou-
ble clocking or mis-clocking, seriously affecting the
accuracy of the RTC. Care needs to be taken in layout
of the RTC circuit to avoid noise pickup. Below in Fig-
ure 19 is a suggested layout for the X1286 or X1288
devices.
The X1 and X2 connections to the crystal are to be
kept as short as possible. A thick ground trace around
the crystal is advised to minimize noise intrusion, but
ground near the X1 and X2 pins should be avoided as
it will add to the load capacitance at those pins. Keep
in mind these guidelines for other PCB layers in the
vicinity of the RTC device. A small decoupling capaci-
tor at the Vcc pin of the chip is mandatory, with a solid
connection to ground.
The X1286 product has a special consideration. The
PHZ/IRQ- pin on the 8-lead SOIC package is located
next to the X2 pin. When this pin is used as a fre-
quency output (PHZ) and is set to 32.768kHz output
frequency, noise can couple to the X1 or X2 pins and
cause double-clocking. The layout in Figure 19 can
help minimize this by running the PHZ output away
Parameter
Min
Typ
Max
Units
Notes
Frequency
32.768
kHz
Freq. Tolerance
±100
ppm
Down to 20ppm if desired
Turnover Temperature
20
25
30
°C
Typically the value used for most
crystals
Operating Temperature Range
-40
85
°C
Parallel Load Capacitance
12.5
pF
Equivalent Series Resistance
50
k
For best oscillator performance
Manufacturer
Part Number
Temp Range
+25°C Freq Toler.
Citizen
CM201, CM202, CM200S
-40 to +85°C
±20ppm
Epson
MC-405, MC-406
-40 to +85°C
±20ppm
Raltron
RSM-200S-A or B
-40 to +85°C
±20ppm
SaRonix
32S12A or B
-40 to +85°C
±20ppm
Ecliptek
ECPSM29T-32.768K
-10 to +60°C
±20ppm
ECS
ECX-306/ECX-306I
-10 to +60°C
±20ppm
Fox
FSM-327
-40 to +85°C
±20ppm
C1
0.1F
XTAL1
U1
R1 10k
X1286/X1288
32.768kGz
FIGURE 19. SUGGESTED LAYOUT FOR INTERSIL RTC IN SO-8
X1288
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