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參數(shù)資料
| 型號： | X1288S16-4.5A |
| 廠商： | Intersil |
| 文件頁數(shù)： | 5/27頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC/CAL/CPU SUP EE 16-SOIC |
| 標(biāo)準(zhǔn)包裝： | 47 |
| 類型： | 時鐘/日歷 |
| 特點(diǎn)： | 警報(bào)器，閏年，監(jiān)控器，監(jiān)視計(jì)時器 |
| 時間格式： | HH:MM:SS:hh（12/24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 管件 |
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13
FN8102.3
April 14, 2006
CONTROL REGISTERS
The Control Bits and Registers, described under this
section, are nonvolatile.
Block Protect Bits - BP2, BP1, BP0
The Block Protect Bits, BP2, BP1 and BP0, determine
which blocks of the array are write protected. A write to a
protected block of memory is ignored. The block protect
bits will prevent write operations to one of eight segments
of the array. The partitions are described in Table 3.
Watchdog Timer Control Bits - WD1, WD0
The bits WD1 and WD0 control the period of the
Watchdog Timer. See Table 4 for options.
Table 3. Block Protect Bits
Table 4. Watchdog Timer Time-Out Options
INTERRUPT CONTROL AND FREQUENCY
OUTPUT REGISTER (INT)
Interrupt Control and Status Bits (IM, AL1E, AL0E)
There are two Interrupt Control bits, Alarm 1 Interrupt
Enable (AL1E) and Alarm 0 Interrupt Enable (AL0E) to
specifically enable or disable the alarm interrupt signal
output (IRQ). The interrupts are enabled when either
AL1E and AL0E are set to ‘1’, respectively.
Two volatile bits (AL1 and AL0), associated with the
two alarms respectively, indicate if an alarm has hap-
pened. These bits are set on an alarm condition
regardless of whether the IRQ interrupt is enabled.
The AL1 and AL0 bits in the status register are reset
by the falling edge of the eighth clock of a read of the
register containing the bits.
Pulse Interrupt Mode
The pulsed interrupt mode allows for repetitive or
recurring alarm functionality. Hence an repetitive or
recurring alarm can be set for every nth second, or nth
minute, or nth hour, or nth date, or for the same day of
the week. The pulsed interrupt mode can be consid-
ered a repetitive interrupt mode, with the repetition
rate set by the time setting fo the alarm.
The Pulse Interrupt Mode is enabled when the IM bit is
set.
The Alarm IRQ output will output a single pulse of
short duration (approximately 10-40ms) once the
alarm condition is met. If the interrupt mode bit (IM bit)
is set, then this pulse will be periodic.
Programmable Frequency Output Bits - FO1, FO0
These are two output control bits. They select one of
three divisions of the internal oscillator, that is applied
to the PHZ output pin. Table 5 shows the selection bits
for this output. When using the PHZ output function,
the Alarm IRQ output function is disabled.
Table 5. Programmable Frequency Output Bits
ON-CHIP OSCILLATOR COMPENSATION
Digital Trimming Register (DTR) - DTR2, DTR1 and
DTR0 (Non-Volatile)
The digital trimming Bits DTR2, DTR1 and DTR0
adjust the number of counts per second and average
the ppm error to achieve better accuracy.
DTR2 is a sign bit. DTR2=0 means frequency
compensation is > 0. DTR2=1 means frequency
compensation is < 0.
DTR1 and DTR0 are scale bits. DTR1 gives 10 ppm
adjustment and DTR0 gives 20 ppm adjustment.
A range from -30ppm to +30ppm can be represented
by using three bits above.
BP2
BP1
BP0
Protected
Addresses
X1288
Array Lock
0
None
None (default)
0
1
6000h – 7FFFh
Upper 1/4
0
1
0
4000h – 7FFFh
Upper 1/2
0
1
0000h – 7FFFh
Full Array
1
0
0000h – 007Fh
First Page
1
0
1
0000h – 00FFh
First 2 pgs
1
0
0000h – 01FFh
First 4 pgs
1
0000h – 03FFh
First 8 Pgs
WD1 WD0
Watchdog Time-Out Period
0
1.75 seconds
0
1
750 milliseconds
1
0
250 milliseconds
1
Disabled (default)
IM Bit
Interrupt/Alarm Frequency
0
Single Time Event Set By Alarm
1
Repetitive/Recurring Time Event Set By Alarm
FO1
FO0
Output Frequency
(average of 100 samples)
0
Alarm IRQ output
0
1
32.768kHz
1
0
100Hz
11
1Hz
X1288
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