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| 型號： | X1228V14Z-2.7A |
| 廠商： | Intersil |
| 文件頁數(shù)： | 25/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC/CAL/CPU SUP EE 14-TSSOP |
| 標準包裝： | 95 |
| 類型： | 時鐘/日歷 |
| 特點： | 警報器，閏年，監(jiān)控器，監(jiān)視計時器 |
| 時間格式： | HH:MM:SS（12/24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 14-TSSOP |
| 包裝： | 管件 |
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5
FN8100.4
May 18, 2006
Notes: (1) The device enters the Active state after any start, and remains active: for 9 clock cycles if the Device Select Bits in the Slave Address
Byte are incorrect or until 200nS after a stop ending a read or write operation.
(2) The device enters the Program state 200nS after a stop ending a write operation and continues for tWC.
(3) The device goes into the Timekeeping state 200nS after any stop, except those that initiate a nonvolatile write cycle; tWC after a stop
that initiates a nonvolatile write cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave
Address Byte.
(4) For reference only and not tested.
(5) VIL = VCC x 0.1, VIH = VCC x 0.9, fSCL = 400kHz
(6) VCC = 0V
(7) VBACK = 0V
(8) VSDA = VSCL=VCC, Others = GND or VCC
(9) VSDA =VSCL=VBACK, Others = GND or VBACK
(10) VSDA = GND or VCC, VSCL = GND or VCC, VRESET = VCC or GND
(11) IOL = 3.0mA at 5.5V, 1.5mA at 2.7V
(12) IOH = -1.0mA at 5.5V, -0.4mA at 2.7V
(13) Threshold voltages based on the higher of Vcc or Vback.
(14) Using recommended crystal and oscillator network applied to X1 and X2 (25°C).
(15) Typical values are for TA = 25°C
Capacitance TA = 25°C, f = 1.0 MHz, VCC = 5V
Notes: (1) This parameter is not 100% tested.
(2) The input capacitance between x1 and x2 pins can be varied between 5pF and 19.75pF by using analog trimming registers
AC CHARACTERISTICS
AC Test Conditions
Figure 18. Standard Output Load for testing the device with VCC = 5.0V
Symbol
Parameter
Max.
Units
Test Conditions
COUT(1)
Output Capacitance (SDA, PHZ/IRQ, RESET)10
pF
VOUT = 0V
CIN(1)
Input Capacitance (SCL)
10
pF
VIN = 0V
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
Input Rise and Fall Times
10ns
Input and Output Timing
Levels
VCC x 0.5
Output Load
Standard Output Load
SDA
1533
Ω
100pF
5.0V
For VOL= 0.4V
and IOL = 3 mA
Equivalent AC Output Load Circuit for VCC = 5V
1316
Ω
5.0V
PHZ/IRQ
100pF
806
Ω
X1228
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