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參數(shù)資料
| 型號： | X1227V8Z-2.7A |
| 廠商： | INTERSIL CORP |
| 元件分類： | XO, clock |
| 英文描述： | RTC Module With CPU Supervisor |
| 中文描述： | 1 TIMER(S), REAL TIME CLOCK, PDSO8 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MO-153AC, TSSOP-8 |
| 文件頁數(shù)： | 6/28頁 |
| 文件大?。?/td> | 442K |
| 代理商： | X1227V8Z-2.7A |
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X1227
REV 1.1.20 1/13/03
Characteristics subject to change without notice.
6 of 28
www.xicor.com
until the part powers up again. Writes to WEL bit do
not cause a nonvolatile write cycle, so the device is
ready for the next operation immediately after the stop
condition.
RTCF: Real Time Clock Fail Bit—Volatile
This bit is set to a ‘1’ after a total power failure. This is
a read only bit that is set by hardware (X1227 inter-
nally) when the device powers up after having lost all
power to the device. The bit is set regardless of
whether V
CC
or V
BACK
is applied first. The loss of only
one of the supplies does not result in setting the RTCF
bit. The first valid write to the RTC after a complete
power failure (writing one byte is sufficient) resets the
RTCF bit to ‘0’.
Unused Bits:
This device does not use bits 3 or 4 in the SR, but
must have a zero in these bit positions. The Data Byte
output during a SR read will contain zeros in these bit
locations.
CONTROL REGISTERS
The Control Bits and Registers, described under this
section, are nonvolatile.
Block Protect Bits—BP2, BP1, BP0
The Block Protect Bits, BP2, BP1 and BP0, determine
which blocks of the array are write protected. A write to a
protected block of memory is ignored. The block protect
bits will prevent write operations to one of eight segments
of the array. The partitions are described in Table 3 .
Table 3. Block Protect Bits
Watchdog Timer Control Bits—WD1, WD0
The bits WD1 and WD0 control the period of the
Watchdog Timer. See Table 4 for options.
Table 4. Watchdog Timer Time-Out Options
ON-CHIP OSCILLATOR COMPENSATION
Digital Trimming Register (DTR) — DTR2, DTR1
and DTR0 (Non-Volatile)
The digital trimming Bits DTR2, DTR1 and DTR0
adjust the number of counts per second and average
the ppm error to achieve better accuracy.
DTR2 is a sign bit. DTR2=0 means frequency
compensation is > 0. DTR2=1 means frequency
compensation is < 0.
DTR1 and DTR0 are scale bits. DTR1 gives 10 ppm
adjustment and DTR0 gives 20 ppm adjustment.
A range from -30ppm to +30ppm can be represented
by using three bits above.
Table 5. Digital Trimming Registers
B
B
B
Protected Addresses
X1227
None (Default)
180
h
– 1FF
100
h
– 1FF
000
h
– 1FF
000
h
– 03F
000
h
– 07F
000
h
– 0FF
000
h
– 1FF
Array Lock
None
Upper 1/4
0
0
0
0
0
1
h
0
1
0
h
Upper 1/2
0
1
1
h
Full Array
1
0
0
h
First Page
1
0
1
h
First 2 pgs
1
1
0
h
First 4 pgs
1
1
1
h
First 8 pgs
WD1 WD0
0
0
1
1
Watchdog Time-Out Period
0
1
0
1
1.75 seconds (Factory Default)
750 milliseconds
250 milliseconds
Disabled
DTR Register
DTR2
DTR1
0
0
0
0
1
1
1
1
Estimated frequency
PPM
0 (Default)
+10
+20
+30
0
-10
-20
-30
DTR0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
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