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參數(shù)資料
| 型號： | X1227S8IZ-2.7A |
| 廠商： | INTERSIL CORP |
| 元件分類： | XO, clock |
| 英文描述： | RTC Module With CPU Supervisor |
| 中文描述： | 1 TIMER(S), REAL TIME CLOCK, PDSO8 |
| 封裝： | ROHS COMPLIANT, PLASTIC, SOIC-8 |
| 文件頁數(shù)： | 7/28頁 |
| 文件大小： | 442K |
| 代理商： | X1227S8IZ-2.7A |
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X1227
REV 1.1.20 1/13/03
Characteristics subject to change without notice.
7 of 28
www.xicor.com
Analog Trimming Register (ATR) (Non-volatile)
Six analog trimming Bits from
vided to adjust the on-chip loading capacitance range.
The on-chip load capacitance ranges from 3.25pF to
18.75pF. Each bit has a different weight for capaci-
tance adjustment. Using a Citizen CFS-206 crystal
with different ATR bit combinations provides an esti-
mated ppm range from +116ppm to -37ppm to the
nominal frequency compensation. The combination of
digital and analog trimming can give up to +146ppm
adjustment.
ATR5
to
ATR0
are pro-
The on-chip capacitance can be calculated as follows:
C
ATR
= [(ATR value, decimal) x 0.25pF] + 11.0pF
Note that the ATR values are in two’s complement,
with ATR(000000) = 11.0pF, so the entire range runs
from 3.25pF to 18.75pF in 0.25pF steps.
The values calculated above are typical, and total load
capacitance seen by the crystal will include approxi-
mately 2pF of package and board capacitance in addi-
tion to the ATR value.
See Application section and Xicor’s Application Note
AN154 for more information.
WRITING TO THE CLOCK/CONTROL REGISTERS
Changing any of the nonvolatile bits of the clock/con-
trol register requires the following steps:
– Write a 02h to the Status Register to set the Write
Enable Latch (WEL). This is a volatile operation,
so there is no delay after the write. (Operation
preceeded by a start and ended with a stop).
– Write a 06h to the Status Register to set both the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceeded by a start
and ended with a stop).
– Write one to 8 bytes to the Clock/Control Registers
with the desired clock, alarm, or control data. This
sequence starts with a start bit, requires a slave byte
of “11011110” and an address within the CCR and is
terminated by a stop bit. A write to the CCR changes
EEPROM values so these initiate a nonvolatile write
cycle and will take up to 10ms to complete. Writes to
undefined areas have no effect. The RWEL bit is
reset by the completion of a nonvolatile write cycle,
so the sequence must be repeated to again initiate
another change to the CCR contents. If the
sequence is not completed for any reason (by send-
ing an incorrect number of bits or sending a start
instead of a stop, for example) the RWEL bit is not
reset and the device remains in an active mode.
– Writing all zeros to the status register resets both the
WEL and RWEL bits.
– A read operation occurring between any of the
previous operations will not interrupt the register
write operation.
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