參數(shù)資料
型號: X1226S8ZT1
廠商: INTERSIL CORP
元件分類: XO, clock
英文描述: Real Time Clock/Calendar with EEPROM
中文描述: 1 TIMER(S), REAL TIME CLOCK, PDSO8
封裝: 0.150 INCH, ROHS COMPLIANT, SOIC-8
文件頁數(shù): 2/24頁
文件大小: 420K
代理商: X1226S8ZT1
X1226
REV 1.1.24 1/13/03
Characteristics subject to change without notice.
2 of 24
www.xicor.com
DESCRIPTION
(continued)
The Real-Time Clock keeps track of time with separate
registers for Hours, Minutes, Seconds. The Calendar
has separate registers for Date, Month, Year and Day-
of-week. The calendar is correct through 2099, with
automatic leap year correction.
The powerful Dual Alarms can be set to any Clock/
Calendar value for a match. For instance, every
minute, every Tuesday, or 5:23 AM on March 21. The
alarms can be polled in the Status Register or provide
a hardware interrupt (IRQ Pin). There is a repeat
mode for the alarms allowing a periodic interrupt.
The PHZ/IRQ pin may be software selected to provide
a frequency output of 1 Hz, 4096 Hz, or 32,768 Hz.
The device offers a backup power input pin. This
V
BACK
pin allows the device to be backed up by battery
or SuperCap. The entire X1226 device is fully
operational from 2.7 to 5.5 volts and the clock/calendar
portion of the X1226 device remains fully operational
down to 1.8 volts (Standby Mode).
The X1226 device provides 4K bits of EEPROM with 8
modes of BlockLock control. The BlockLock allows a
safe, secure memory for critical user and configuration
data, while allowing a large user storage area.
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device. The input buffer on this pin is always active
(not gated).
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It has an open drain output and may
be wire ORed with other open drain or open collector
outputs. The input buffer is always active (not gated).
An open drain output requires the use of a pull-up
resistor. The output circuitry controls the fall time of the
output signal with the use of a slope controlled pull-
down. The circuit is designed for 400kHz 2-wire inter-
face speed.
V
This input provides a backup supply voltage to the
device. V
BACK
supplies power to the device in the
event the V
CC
supply fails. This pin can be connected
to a battery, a Supercap or tied to ground if not used.
BACK
Programmable Frequency/Interrupt Output – PHZ/IRQ
This is either an output from the internal oscillator or an
interrupt signal output. It is an open drain output.
When used as frequency output, this signal has a
frequency of 32.768kHz, 4096Hz, 1Hz or inactive.
When used as interrupt output, this signal notifies a
host processor that an alarm has occurred and an
action is required. It is an active LOW output.
The control bits for this function are FO1 and FO0 and
are found in address 0011h of the Clock Control Mem-
ory map. Refer to “Programmable Frequency Output
Bits” on page 6.
X1, X2
The X1 and X2 pins are the input and output,
respectively, of an inverting amplifier. An external
32.768kHz quartz crystal is used with the X1226 to
supply a timebase for the real time clock. The
recommended crystal is a Citizen CFS206-32.768KDZF.
Internal compensation circuitry is included to form a
complete oscillator circuit. Care should be taken in the
placement of the crystal and the layout of the circuit.
Plenty of ground plane around the device and short
traces to X1 and X2 are highly recommended. See
Application section for more recommendations.
Figure 1. Recommended Crystal connection
POWER CONTROL OPERATION
The power control circuit accepts a V
input. The power control circuit powers the clock from
V
BACK
when V
CC
< V
BACK
– 0.2V. It will switch back to
power the device from V
CC
when V
CC
and a V
BACK
CC
exceeds V
BACK
.
NC = No internal connection
X1
X2
V
BACK
V
CC
PHZ/IRQ
SCL
SDA
V
SS
1
2
3
4
7
6
5
8
8-Pin TSSOP
X1226
X1
X2
V
BACK
SCL
SDA
V
CC
PHZ/IRQ
V
SS
1
2
3
4
7
6
5
8
8-Pin SOIC
X1
X2
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