參數(shù)資料
型號(hào)： X1226S8I
英文描述： Real Time Clock/Calendar with EEPROM
中文描述： 實(shí)時(shí)時(shí)鐘/日歷帶有EEPROM
文件頁(yè)數(shù)： 10/24頁(yè)
文件大?。?/td> 420K
代理商： X1226S8I
X1226
REV 1.1.24 1/13/03
Characteristics subject to change without notice.
10 of 24
www.xicor.com
Write Operations
Byte Write
For a write operation, the device requires the Slave
Address Byte and the Word Address Bytes. This gives
the master access to any one of the words in the array
or CCR. (Note: Prior to writing to the CCR, the master
must write a 02h, then 06h to the status register in two
preceding operations to enable the write operation.
See “Writing to the Clock/Control Registers.” Upon
receipt of each address byte, the X1226 responds with
an acknowledge. After receiving both address bytes
the X1226 awaits the eight bits of data. After receiving
the 8 data bits, the X1226 again responds with an
acknowledge. The master then terminates the transfer
by generating a stop condition. The X1226 then begins
an internal write cycle of the data to the nonvolatile
memory. During the internal write cycle, the device
inputs are disabled, so the device will not respond to
any requests from the master. The SDA output is at high
impedance. See Figure 7.
Figure 7. Byte Write Sequence
Figure 8. Writing
30
bytes to a
64
-byte memory page starting at address
40
.
S
t
a
r
t
S
t
o
p
Slave
Address
Word
Address 1
Data
A
C
K
A
C
K
A
C
K
SDA Bus
Signals From
The Slave
Signals from
the Master
0
A
C
K
Word
Address 0
1
1
1
1
0 0 0 0 0 0 0
Address
63
Address
40
23 Bytes
7 Bytes
Address
= 6
Address Pointer
Ends Here
Addr = 7
Figure 6. Slave Address, Word Address, and Data Bytes (64 Byte pages)
Slave Address Byte
Byte 0
D7
D6
D5
D2
D4
D3
D1
D0
A0
A7
A2
A4
A3
A1
Data Byte
Byte 3
A6
A5
0
0
0
0
0
A8
0
1
1
0
1
1
0
1
0
1
1
R/W
1
Device Identifier
Array
CCR
0
Word Address 1
Byte 1
Word Address 0
Byte 2
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