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參數(shù)資料
| 型號： | X1205V8ZT1 |
| 廠商： | INTERSIL CORP |
| 元件分類： | XO, clock |
| 英文描述： | 2-Wire RTC Real Time Clock/Calendar |
| 中文描述： | REAL TIME CLOCK, PDSO8 |
| 封裝： | 4.40 MM, ROHS COMPLIANT, PLASTIC, TSSOP-8 |
| 文件頁數(shù)： | 8/22頁 |
| 文件大小： | 407K |
| 代理商： | X1205V8ZT1 |
PRELMNARY
detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.
X1205 – Preliminary Information
REV 1.0.9 8/29/02
Characteristics subject to change without notice.
8 of 22
www.xicor.com
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
DEVICE ADDRESSING
Following a start condition, the master must output a
Slave Address Byte. Slave bits ‘1101’ access the CCR.
Bit 3 through Bit 1 of the slave byte specify the device
select bits. These are set to ‘111’.
The last bit of the Slave Address Byte defines the oper-
ation to be performed. When this R/W bit is a one, then
a read operation is selected. A zero selects a write
operation. Refer to Figure 6.
After loading the entire Slave Address Byte from the
SDA bus, the X1205 compares the device identifier
and device select bits with ‘1101111’. Upon a correct
compare, the device outputs an acknowledge on the
SDA line.
Figure 3. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable
Data Change
Data Stable
Figure 4. Valid Start and Stop Conditions
SCL
SDA
Start
Stop
Figure 5. Acknowledge Response From Receiver
SCL from
Master
Data Output
from Transmitter
Data Output
from Receiver
8
1
9
Start
Acknowledge
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