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參數(shù)資料
| 型號(hào)： | X1205S8ZT1 |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 4/22頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC/CALENDAR/ALARM 4K 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘/日歷 |
| 特點(diǎn)： | 警報(bào)器，閏年 |
| 時(shí)間格式： | HH:MM:SS（12/24 小時(shí)） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 剪切帶 (CT) |
| 其它名稱： | X1205S8ZT1CT |
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12
FN8097.3
May 2, 2006
byte are required. (Operation preceeded by a start
and ended with a stop).
– Write one to 8 bytes to the Clock/Control Registers
with the desired clock, alarm, or control data. This
sequence starts with a start bit, requires a slave byte
of “11011110” and an address within the CCR and is
terminated by a stop bit. A write to the CCR changes
nonvolatile register values so these initiate a non-
volatile write cycle and will take up to 10ms to com-
plete. Writes to undefined areas have no effect. The
RWEL bit is reset by the completion of a nonvolatile
write cycle, so the sequence must be repeated to
again initiate another change to the CCR contents.
If the sequence is not completed for any reason
(by sending an incorrect number of bits or sending a
start instead of a stop, for example) the RWEL bit is
not reset and the device remains in an active mode.
– Writing all zeros to the status register resets both the
WEL and RWEL bits.
– A read operation occurring between any of the previ-
ous operations will not interrupt the register write
operation.
SERIAL COMMUNICATION
Interface Conventions
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this fam-
ily operate as slaves in all applications.
Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 3.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met. See Figure 4.
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
when SCL is HIGH. The stop condition is also used to
place the device into the Standby power mode after a
read sequence. A stop condition can only be issued
after the transmitting device has released the bus. See
Figure 4.
Acknowledge
Acknowledge is a software convention used to indi-
cate successful data transfer. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 6.
The device will respond with an acknowledge after
recognition of a start condition and if the correct
Device Identifier and Select bits are contained in the
Slave Address Byte. If a write operation is selected,
the device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for:
– The Slave Address Byte when the Device Identifier
and/or Select bits are incorrect
– All Data Bytes of a write when the WEL in the Write
Protect Register is LOW
– The 2nd Data Byte of a Status Register Write
Operation (only 1 data byte is allowed)
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.
X1205
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